Preliminary Specification
CMOS LSI
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M(512K×8bits, 256K×16bits) Flash EEPROM
Features
CMOS Flash EEPROM Technology
Single Voltage Read and Write Operations
LE28FV4101
: 3.0V
~
3.6V
LE28F
W
4101
: 2.7V
~
3.6V
LE28FU4101
: 2.3V
~
3.6V
Sector Erase Capability: 1kWord per sector
: (2kByte per sector)
Block Erase Capability: 32kWord per Block
: (64kByte per Block)
Fast Access Time
LE28FV4101T,H-40T :40ns(Max.)
LE28FV4101T,H-50T :50ns(Max.)
LE28FV4101T,H-70T :70ns(Max.)
LE28FW4101T,H-45T :45ns(Max.)
LE28FW4101T,H-55T :55ns(Max.)
LE28FW4101T,H-70T :70ns(Max.)
LE28FU4101T,H-70T :70ns(Max.)
LE28FU4101T,H-85T :85ns(Max.)
LE28FU4101T,H-10T :100ns(Max.)
Low Power Consumption
Active Current (Read) : 40 mA (Max.)
Standby Current
: 40
µ
A (Max.)
High Read/Write Reliability
Sector-write Endurance Cycles: 10
4
10 Years Data Retention
Latched Address and Data
Self-timed Erase and Programming
Word Programming
LE28FV/FW4101
: 20
µ
s (Max.)
LE28FU4101
: 30
µ
s (Max.)
End of Write Detection
:Toggle Bit , DATA# Polling
:RD/BY#
Hardware/Software Data Protection
Protected cell area
:
Top Block(16K-Bytes from the top address)
Whole chip(512K-Bytes)
Packages Available :
LE28FV,FW,FU4101T :TSOP-48 (12mm x 20mm)
LE28FV,FW,FU4101H :FLGA-52 (6mm x 6mm)
Product Description
The LE28FV4101/LE28FW4101/LE28FU4101 is a 256K
×16
or 512K
×8
CMOS sector erase, Word(Byte) program
EEPROM.
The LE28FV4101/LE28FW4101/LE28FU4101 is manu-
factured using SANYO's proprietary, high performance
CMOS Flash EEPROM technology. Breakthroughs in
EEPROM cell design and process architecture attain better
reliability and manufacturability compared with conven-
tional approaches.
LE28FV4101/LE28FW4101/LE28FU4101 erases and pro-
grams with single power supply.
LE28FV4101/LE28FW4101/LE28FU4101 is offered in
FLGA52 (6mm x 6mm) packages and TSOP48(12mm x
20mm) package.
Featuring high performance programming,
LE28FV4101/LE28FW4101/LE28FU4101 programs in
20µs/30µs(max). The
LE28FV4101/LE28FW4101/LE28FU4101 sector (1k
Words) erases in 25ms(Max.). Both program and erase times
can be optimized using interface feature such as Toggle bit,
DATA# Polling or RD/BY# to indicate the completion of
the write cycle. To protect against an inadvertent write, the
LE28FV4101/LE28FW4101/LE28FU4101 has on chip
hardware and software data protection schemes. Designed,
manufactured, and tested for a wide spectrum of applications,
LE28FV4101/LE28FW4101/LE28FU4101 is offered with a
guaranteed sector write endurance of 10
4
cycles. Data reten-
tion is rated greater than 10 years.
Device Operation
The LE28FV4101/LE28FW4101/LE28FU4101 operates
random read, Word(Byte)-program, sector or block or
Chip-erase flash memory.
The Self-Power Conservation feature automatically puts the
LE28FV4101/LE28FW4101/LE28FU4101 in a low power
mode after data has been accessed with a valid read opera-
tion. This reduces the I
DD
active read current from
40mA(Max) to 300µA(Typ.). The device exits the Self
Power Conservation mode with any address transition or
control signal transition used to initiate another read cycle,
with no access time penalty.
*This product incorporate technology licensed from Silicon Storage Technology, Inc.
This preliminary specification is subject to change without notice.
SANYO Electric Co., Ltd. Semiconductor Company
1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN
Revision 6.0 Mar. 28 2001 -AY/ay
-1/26
Preliminary Specification
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
Standby
Standby mode reduces current consumption greatly with the
Output pins in High-Impedance state. By setting both of
CE# and RESET# to VDD ±0.3V ,otherwise RESET# to
VSS ±0.3V, device enter the standby mode.
Standby mode cannot be set when the device is not in read
mode.( i.e Erase or Program mode)
Chip-Erase
The LE28FV4101/LE28FW4101/LE28FU4101 provides a
chip-erase mode, which allows the user to clear the Flash
array to the “1” state. This is useful when the entire de-
vice must be quickly erased.
The chip erase mode is initiated by issuing the specific six-
Word loading sequence, as in the Software Data Protection
operation. After the loading cycle, the device enters into an
internally timed cycle. See Table 3 for specific codes, Fig-
ure 13~16 for the timing waveform, and Figure 32 for a
flowchart.
Read
The read operation is controlled by CE# and OE#, a chip
enable and output enable both have to be low for the system
to obtain data from the outputs. When CE# is high, the chip
is deselected. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when OE# is high. Refer to the timing waveforms
for further details (Figure 3~4).
Block-Erase
The LE28FV4101/LE28FW4101/LE28FU4101 provides a
block-erase mode.
Block-Erase mode is based on uniform Block size of
32KWord(64kByte), which allows the user to clear any
block in the Flash array to the “1” state.
The block-erase mode is initiated by issuing the specific
six-Word loading sequence, as in the Software Data Protect
operation. After the loading cycle, the device enters into an
internally timed erase cycle. See Table 3 for specific codes,
Figure 13~16 for the timing waveform, and Figure 31 for a
flowchart.
Write
All write operations are initiated by the JEDEC approved
Software Data Protect (SDP) entry sequence, for
Chip_Erase, Block_Erase, Sector_Erase and Program. Pro-
gram and all erase commands have a fixed duration, that
will not vary over the life of the device, i.e., are indepen-
dent of the number of erase/program cycles endured.
The device is always in the Software Data Protected mode
for all Write operations. Write operations are controlled by
toggling of WE# or CE#. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first. After SDP sequence, the device
enter the selected mode automatically. When the wrong
address or data are offered, the device interrupt the SDP
mode at once and go back to read mode. See Figure 5~8 for
the timing waveform.
Sector-Erase
The LE28FV4101/LE28FW4101/LE28FU4101 provides a
sector-erase mode
Sector-Erase mode is based on uniform sector size of
1kWord(2kByte), which allows the user to clear any sector
in the Flash array to the “1” state.
The sector-erase mode is initiated by issuing the specific
six-Word loading sequence, as in the Software Data Protect
operation. After the loading cycle, the device enters into an
internally timed erase cycle. See Table 3 for specific codes,
Figure 13~16 for the timing waveform, and Figure 30 for a
flowchart.
Program
The program operation consists of issuing the SDP program
command.
Its command can be to program value to one address in
memory cell array at a time. The command require 4-bus
cycle operation, the final write operation latches the address
and data in the internal state machine. Programming opera-
tion starts with either the rising of WE#, CE#, whichever
occurs first. The Program operation, once initiated, will be
completed within 20µs(30µs).
See Figure 17~20 program cycle timing waveform, Table 3
for the command sequence, and Figure 33 for a Flowchart.
Note that the Program command cannot change a bit set at
“0” back to “1”. One of the Erase command must be used to
the all bit in sector ,Block or in the whole memory from “0”
to “1”.
Chip Protection , Block Protection /
Un-protection
Chip Protection and Block Protection disables both pro-
gram and erase operation.
Chip Protection defends from inadvertent write in the whole
memory, and consists of issuing the SDP command.
Block Protection defends 8kWord(16kByte) Top Block
from inadvertent write, and consists of issuing the SDP
command.
Un-protection can be canceling both Chip Protection and
Block Protection, and consists of issuing the SDP command.
2/26
SANYO Electric Co., Ltd.
Preliminary Specification
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
See Table 3 for specific codes, Figure 21~22 for the timing
waveform.
Toggle Bit (DQ
6
)
During the Flash internal write cycle, any consecutive at-
tempts to read DQ
6
will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is com-
pleted, the toggling will stop. The device is then ready for
the next operation. See Figure 29 for Flash Toggle Bit
timing waveforms.
Protect Verification
Protect Verification mode indicate Chip Protection or
Block Protection status, consists of issuing the SDP com-
mand. See Table 3 for specific codes.
To verify which protect mode the device is in, read follow-
ing addresses and the data shows the protect mode. i.e.
Address(0004H:Byte mode,0002H Word mode) ,
Data(01H:Byte mode,0001H: Word mode) shows sector
protect.
Address(0004H:Byte mode,0002H: Word mode),
Data(00H:Byte mode,0000H: Word mode) shows unprotect.
Address(0006H:Byte mode,0003H Word mode),
Data(01H:Byte mode,0001H Word mode) shows chip pro-
tect.
Address(0006H:Byte mode,0003H: Word mode),
Data(00H:Byte mode,0000H Word mode) shows unprotect.
In order to return to the standard read mode, the Protect
Verification mode must be exited. Exit is accomplished by
issuing the Read/Reset command, which returns the device
to normal operation.
RD/BY#
LE28FV4101/LE28FW4101/LE28FU4101 has RD/BY#
pin to be able to detect the completion of a Write cycle.
Output form of RD/BY# pin is internally connected to the
open drained transistor. When the pin is at "L", the device
is busy for a write cycle. When the pin is at "High-Z", the
device is ready for accepting commands. Because of
RD/BY# pin being open drain, User needs to connect a pull
up resistor between RD/BY# pin and VDD. If User use a
number of Flash memories, User may as well connect the
pull up resistor to the memories in parallel.
See Figure 26~27 for RD/BY# timing waveforms.
Data Protection
The LE28FV4101/LE28FW4101/LE28FU4101 provides
both hardware and software features to protect nonvolatile
data from inadvertent writes.
Write Operation Status Detection
The LE28FV4101/LE28FW4101/LE28FU4101 provides
two software means to detect the completion of write cycle,
in order to optimize the system write cycle time. The soft-
ware detection includes two status bits: DATA# Polling
(DQ
7
) and Toggle Bit (DQ
6
). The end of write detection
mode is enabled after the rising edge of WE#, which initi-
ates the internal write, erase, or program cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a DATA# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system will possibly
get an erroneous result, i.e. valid data may appear to con-
flict with either DQ
7
or DQ
6
. In order to prevent spurious
device rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location
an additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Hardware Data Protection
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation.
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a write cycle.
V
DD
Power Up/Down Detection: Immediately after the
power-up, the device is in read mode. The write operation
is inhibited when VDD is less than 1.5 volts. This prevents
inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The LE28FV4101/LE28FW4101/LE28FU4101 provide the
JEDEC approved software data protection scheme as a
requirement for initiating a Write, Erase, or Program op-
eration. With this scheme, any write operation requires the
inclusion of a series of three Cycle-load operations to
precede the Word program operation. The three Cycle-load
sequence is used to initiate the program cycle, providing
optimal protection from inadvertent write operations, e.g.,
during the system power-up or power-down. The six-Cycle
Sequence is required to initiate any chip, block, or sector
erase operation.
The requirements for JEDEC compliant SDP are in Byte
formats. The LE28FV4101/LE28FW4101/LE28FU4101
are organized by Word; therefore, the contents of DQ
8
to
DQ
15
are “Don’t care” during any SDP (3-Cycle or 6-
Cycle) command sequence.
DATA# Polling (DQ
7
)
When the LE28FV4101/LE28FW4101/LE28FU4101 is in
the internal Flash write cycle, any attempt to read DQ
7
of
the last Word loaded during the Flash Word-load cycle will
receive the complement of the true data. Once the write
cycle is completed, DQ
7
will show true data. The device is
then ready for the next operation. See Figure 28 for Flash
DATA# Polling timing waveforms.
SANYO Electric Co., Ltd.
3/26
Preliminary Specification
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur during the SDP load sequence.
Read/RESET
In order to return to the standard read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Read/Reset command, which returns the device
to normal operation. This command may also be used to
reset the device to the read mode after any inadvertent tran-
sient condition that apparently causes the device to behave
abnormally, e.g., not read correctly.
Immediately after the power-up, device should be set to read
mode without using READ/RESET command.
For details, see
Table 3 for software operation and Figures 9~12 for timing
waveforms.
Hardware RESET
To quit the Erase or Program operation, LE28FV4101/
LE28FW4101/ LE28FU4101 can be reset by forcing RE-
SET# pin into low. After receiving RESET# pulse, the
device begins Reset operation and terminates the Reset
operation 10µs(max) later. After the hardware reset opera-
tion, all output pins are in high-impedance state when
RESET# is “L”, or device is in read mode after the period
of tRST by setting RESET# pin “H”.
Product Identification
The product identification mode identifies the device manu-
facturer as SANYO. Users may wish to use the device ID
operation to identify the write algorithm requirements. For
details, see Table 3 for software operation and Figures
23~24 for timing waveforms.
Decoupling Capacitors
Ceramic capacitor (0.1µF) must be added between V
DD
and V
SS
for each device to assure stable flash memory op-
eration.
The attention to the usage of this LSI
For the reasons of using ATD (Address Transition De-
tector) Circuit, the output data of this LSI directly after
supplying voltage, program operation or erase operation are
invalid. The valid data would be offered after the transition
of at least one of CE# or address signals under the stable
voltage.
In case of power on, We recommend to input “RESET#”
signal in order to do initial the internal circuit.
Figure1: Pin Connection
TSOP-48(12mm x 20mm)
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
NC
NC
W E#
R ESET#
NC
NC
R D /B Y #
NC
A 17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Top View )
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A 16
B Y TE#
V ss
D Q15/A -1
D Q7
D Q14
D Q6
D Q13
D Q5
D Q12
D Q4
V
D D
D Q11
D Q3
D Q10
D Q2
D Q9
D Q1
D Q8
D Q0
O E#
V ss
C E#
A0
SANYO Electric Co., Ltd.
4/26
Preliminary Specification
LE28FV4101T,H-40T/50T/70T
LE28FW4101T,H-45T/55T/70T
LE28FU4101T,H-70T/85T/10T
4M-Bit Flash EEPROM
FLGA-52(6mm x 6mm) Top View
(Land facing down)
H
NC
G
A7
F
NC
E
NC
D
RESET#
C
NC
B
A9
A
NC
1
2
3
4
5
6
7
8
A5
A6
A17
NC
WP#
NC
A8
A10
A11
A3
A4
RD/BY#
A12
A13
A1
A2
NC
NC
A14
A15
A0
CE#
OE#
DQ8
NC
NC
BYTE#
A16
VSS
DQ10
DQ12
DQ15
VSS
DQ0
DQ9
DQ3
DQ4
DQ13
DQ14
DQ7
NC
DQ1
DQ2
DQ11
VDD
DQ5
DQ6
NC
Figure2: Functional Block Diagram
A17-A0
Add Buff
&
Latches
X-Decoder
Memory Cell Array
Y-Decoder
CE#
OE#
WE#
Control Logic
I/O Buff &
Data Latches
BYTE#
RESET# RD/BY#
DQ15/A-1
DQ14~DQ0
SANYO Electric Co., Ltd.
5/26
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