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P4C1981L-25FMB

Description
Standard SRAM, 16KX4, 25ns, CMOS, CDFP28, CERPACK-28
Categorystorage    storage   
File Size332KB,13 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1981L-25FMB Overview

Standard SRAM, 16KX4, 25ns, CMOS, CDFP28, CERPACK-28

P4C1981L-25FMB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDFP
package instructionCERPACK-28
Contacts28
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time25 ns
JESD-30 codeR-GDFP-F28
JESD-609 codee0
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width4
Number of functions1
Number of terminals28
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize16KX4
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Filter levelMIL-STD-883 Class B
Maximum seat height2.286 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width9.017 mm
P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
Output Enable and Dual Chip Enable Functions
5V ± 10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C1981L/1982L Military)
Separate Inputs and Outputs
– P4C1981/L Input Data at Outputs during Write
– P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when
OE
is low; the outputs
of the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V ± 10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is
typically 10 µA from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption. For the
P4C1982L and P4C1981L, power is only 5.5 mW standby
with CMOS input levels.
The P4C1981/L and P4C1982/L are available in 28-pin 300
mil DIP and SOJ, 28-pin 350x550 mil LCC and a 28-pin
CERPACK package providing excellent board level den-
sities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5, D5-2), SOJ (J5)
CERPACK (F4) SIMILAR
P4C1981/ 1982
LCC (L5)
Document #
SRAM114
REV B
1
Revised August 2006
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