H5DU5162EFR-E3L datasheet, PDF

H5DU5162EFR-E3L: DescriptionDDR DRAM, 32MX16, 0.7ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60; Categorystorage storage; File Size365KB，31 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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H5DU5162EFR-E3L Overview

DDR DRAM, 32MX16, 0.7ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	VBGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
length	12 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VBGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.005 A
Maximum slew rate	0.26 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	8 mm

512Mb DDR SDRAM

H5DU518(6)2EFR-xxC

H5DU518(6)2EFR-xxI

H5DU518(6)2EFR-xxL

H5DU518(6)2EFR-xxJ

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.2 / Aug. 2011

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