V55C2256164VB
256Mbit MOBILE SDRAM
2.5 VOLT FBGA PACKAGE 16M X 16
7
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
Clock Access Time (t
AC1
) CAS Latency = 1
143 MHz
7 ns
5.4 ns
6 ns
19 ns
8PC
125 MHz
8 ns
6 ns
6 ns
19 ns
10
100MHz
10 ns
7 ns
8 ns
22 ns
Features
■
4 banks x 4Mbit x 16 organization
■
High speed data transfer rates up to 143 MHz
■
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■
Single Pulsed RAS Interface
■
Data Mask for Read/Write Control
■
Four Banks controlled by BA0 & BA1
■
Programmable CAS Latency:1, 2, 3
■
Programmable Wrap Sequence: Sequential or
Interleave
■
Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■
Multiple Burst Read with Single Write Operation
■
Automatic and Controlled Precharge Command
■
Random Column Address every CLK (1-N Rule)
■
Power Down Mode and Clock Suspend Mode
■
Deep Power Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 8192 cycles/64 ms
■
Available in 54-ball FBGA, with 9x6 ball array
with 3 depupulated rows, 13x8 mm and 54 pin
TSOP II
■
VDD=2.5V, VDDQ=1.8V
■
Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■
Operating Temperature Range
Commercial (
0°C to 70°C)
Industrial
(-40°C to +85°C)
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
-40°C to 85°C
Package Outline
C/T
•
•
Access Time (ns)
7
•
•
8PC
•
•
10
•
•
Temperature
Mark
Commercial
Industrial
V55C2256164VB Rev. 1.2 May 2007
1
ProMOS TECHNOLOGIES
Description
V55C2256164VB
The V55C2256164VB is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The
V55C2256164VB achieves high speed data transfer rates up to 143 MHz by employing a chip architecture
that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-
ternally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
CLK
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)
when sampled at the rising clock edge.CAn depends from the SDRAM organization:
• 8M x 16 SDRAM CA0–CA8.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
CS
Input
Pulse
RAS, CAS
WE
A0 - A12
Input
Pulse
Input
Level
BA0,
BA1
DQx
Input
Level
—
Selects which bank is to be active.
Input
Output
Input
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQM
UDQM
Pulse
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.
Power and ground for the input buffers and the core logic.
VCC, VSS
VCCQ
VSSQ
Supply
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V55C2256164VB Rev. 1.2 May 2007
5
FPGA/CPLD
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