EC1325HSETTS-1.544M
EC13 25 HS ET
Series
RoHS Compliant (Pb-free) 3.3V 8 Pin DIP Metal
Thru-Hole LVCMOS/TTL Oscillator
Frequency Tolerance/Stability
±25ppm Maximum
Package
Operating Temperature Range
-40°C to +85°C
RoHS
Pb
Nominal Frequency
1.544MHz
TS -1.544M
Pin 1 Connection
Tri-State (High Impedance)
Duty Cycle
50 ±10(%)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
1.544MHz
±25ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C,
Shock, and Vibration)
±5ppm/year Maximum
-40°C to +85°C
3.3Vdc ±0.3Vdc
10mA Maximum
2.4Vdc Minimum with TTL Load, 2.7Vdc Minimum with LVCMOS Load
0.4Vdc Maximum with TTL Load or 0.5Vdc Maximum with LVCMOS Load
10nSec Maximum (0.4Vdc to 2.4Vdc with TTL Load, or 10% to 90% of waveform with LVCMOS Load)
50 ±10(%) (Measured at 50% of waveform)
2TTL Load or 15pF LVCMOS Load Maximum
CMOS
Tri-State (High Impedance)
+2.2Vdc Minimum to enable output, +0.8Vdc Maximum to disable output (High Impedance), No Connect to
enable output.
±100pSec Maximum
±25pSec Maximum
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Lead Integrity
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2004
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev P 2/17/2010 | Page 1 of 7
EC1325HSETTS-1.544M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
CONNECTION
Tri-State (High
Impedance)
Ground/Case Ground
Output
Supply Voltage
7.620 ±0.203
1
7.620
±0.203 8
4
5
DIA 0.457
±0.1 (X4)
0.8 ±0.1 (X3)
1
4
5
8
LINE MARKING
5.08 MIN
5.6 MAX
13.2
MAX
MARKING
ORIENTATION
1
2
3
4
ECLIPTEK
EC13TS
EC13=Product Series
1.544M
XXYZZ
XX=Ecliptek Manufacturing
Code
Y=Last Digit of the Year
ZZ=Week of the Year
13.2
MAX
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
90% or 2.4V
DC
50% or 1.4V
DC
10% or 0.4V
DC
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
www.ecliptek.com | Specification Subject to Change Without Notice | Rev P 2/17/2010 | Page 2 of 7
EC1325HSETTS-1.544M
Test Circuit for TTL Output
Output Load
Drive Capability
10TTL
5TTL
2TTL
10LSTTL
1TTL
R
L
Value
(Ohms)
390
780
1100
2000
2200
C
L
Value
(pF)
15
15
6
15
3
Oscilloscope
Frequency
Counter
Table 1: R
L
Resistance Value and C
L
Capacitance
Value Vs. Output Load Drive Capability
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
R
L
(Note 4)
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
+
0.01µF
(Note 1)
0.1µF
(Note 1)
C
L
(Note 3)
Power
Supply
_
Ground
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Note 4: Resistance value R
L
is shown in Table 1. See applicable specification sheet for 'Load Drive Capability'.
Note 5: All diodes are MMBD7000, MMBD914, or equivalent.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev P 2/17/2010 | Page 3 of 7
EC1325HSETTS-1.544M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev P 2/17/2010 | Page 4 of 7
EC1325HSETTS-1.544M
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
High Temperature Solder Bath (Wave Solder)
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
3°C/second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev P 2/17/2010 | Page 5 of 7
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