This X24641 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
X24641
64K
FEATURES
•1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Operation
•Low Power CMOS
—Active read current less than 1mA
—Active write current less than 3mA
—Standby current less than 1µA
•400KHz Fast Mode 2-Wire Serial Interface
—Down to 1.8V
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
400 KHz 2-Wire Serial E
2
PROM
DESCRIPTION
8K x 8 Bit
The X24641 is a CMOS Serial E
2
PROM Memory,
internally organized 8K x 8. The device features a serial
interface and software protocol allowing opera-
tion on a simple two wire bus. The bus operates at
400KHz all the way down to 1.8V.
Three device select inputs (S–S
2) allow up to eight
0
devices to share a common two wire bus.
Hardware Write Protection is provided through a Write
Protect (WP) input pin on the X24641. When the WP
pin is HIGH, the upper quadrant of the Serial E
2
PROM
array is protected against any nonvolatile write
attempts.
•Internally Organized 8K x 8
•32 Byte Page Write Mode
—Minimizes total write time per byte
•Hardware Write Protect •Bidirectional
Data Transfer Protocol
•Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
•High Reliability
—Endurance: 1,000,000 cycles
—Data retention: 100 years
Xicor Serial E
2
PROM Memories are designed and
tested for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
•8-Lead SOIC
BLOCK DIAGRAM
Serial E
2
PROM Data
and Address (SDA)
Command
Decode
Data Register
Y Decode Logic
SCL
and
Control
Logic
Page
Decode
Logic
S
2
S
1
S
0
Device
Select
Logic
Write
Protect
Logic
E
2
PROM
Array
8K x 8
WP
Write Voltage
Control
∧
Xicor, Inc. 2000 Patents Pending
7026 10/27/00 EP
Characteristics subject to change without notice.
1 of 14
X24641
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
PIN NAMES
Symbol
S
0
, S
1
, S
2
SDA
SCL
WP
V
SS
V
CC
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
An open drain output requires the use of a pull-up resis- tor.
For selecting typical values, refer to the Pull-up
PIN CONFIGURATION
8-Lead SOIC
S
0
S
1
S
2
V
CC
resistor selection graph at the end of this data sheet.
Device Select (S
0
, S
1
, S
2
)
The device select inputs (S
0
, S
1
, S
2
) are used to set the
first three bits of the 8-bit slave address. This allows up
to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
SS
or V
CC
as appropri-
ate. If actively driven, they must be driven with CMOS
levels.
1
2
3
4
X24641
8
7
6
5
V
CC
WP
SCL
SDA
DEVICE OPERATION
The device supports a bidirectional, bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write Pro-
tection is disabled and the device can be written nor-
mally. When this input is held HIGH, Write Protection is
enabled, and nonvolatile writes are disabled to the
upper quadrant of the E
2
PROM array.
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to
Figures 1 and 2.
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Characteristics subject to change without notice.
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X24641
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
both the device and a Write Operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
return the device to the standby power mode and
to
any command until this condition has been met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
device into the standby power mode after a read
the
sequence. A stop condition can only be issued after the
transmitting device has released the bus.
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL From
Master
1
8
9
Data Output
From Transmitter
Data Output
From Receiver
START
Acknowledge
Characteristics subject to change without notice.
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X24641
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
Figure 4. Device Addressing
Device Type
Identifier
Device
Select
device select bits S
0
, S
1
, and S
2
. This allows up to 8
devices to share a single bus. These bits are compared to
the S
0
, S
1
, and S
2
device select input pins. The last bit
of the Slave Address Byte defines the operation to be
performed. When the R/W bit is a one, then a Read
Operation is selected. When it is zero then a Write
Operation is selected. Refer to Figure 4. After loading
the Slave Address Byte from the SDA bus, the device
compares the device type bits with the value “1010”
1
0
1
0
S
2
S
1
S
0
R/W
SLAVE ADDRESS BYTE
High Order Word Address
0
0
0
A12
A11 A10
A9
A8
and the device select bits with the status of the device
select input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and the
device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
ADDRESS BYTE 1
Low Order Address
operation. When required, the master must supply the
two Address Bytes as shown in Figure 4.
A7
A6
A5
A4
A3
A2
A1
A0
ADDRESS BYTE 0
The internal organization of the E
PROM array is 256
pages by 32 bytes per page. The page address is par-
tially contained in the Address Byte 1 and partially in
2
bits 7 through 5 of the Address Byte 0. The specific
byte address is contained in bits 4 through 0 of the
D7
D6
D5
D4
D3
D2
D1
D0
Address Byte 0. Refer to Figure 4.
DATA BYTE
Characteristics subject to change without notice.
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X24641
WRITE OPERATIONS
Byte Write
For a Byte Write Operation, the device requires the
Slave Address Byte, the Word Address Byte 1, and the
Page Write Operation
The device executes a thirty-two byte Page Write
Operation. For a Page Write Operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the page to be written. Upon receipt of Address
Byte 0, the device responds with an acknowledge, and
waits for the first eight bits of data. After receiving the 8 bits
of the first data byte, the device again responds
Word Address Byte 0, which gives the master access to
any one of the bytes in the array. Upon receipt of the
Word Address Byte 0, the device responds with an
acknowledge, and waits for the first eight bits of data.
After receiving the 8 bits of the data byte, the device
again responds with an acknowledge. The master then
with an acknowledge. The device will respond with an
acknowledge after the receipt of each of 31 more
bytes. Each time the byte address is internally incre-
mented by one, while page address remains constant.
When the counter reaches the end of the page, the
master terminates the data loading by issuing a stop
condition, which causes the device to begin the nonvol-
atile write cycle. All inputs are disabled until completion
of the nonvolatile write cycle. The SDA pin is at high
impedance. Refer to Figure 5 for the address, acknowl-
terminates the transfer by generating a stop condition, at
which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write cycle is
in progress the device inputs are disabled and the
device will not respond to any requests from the master.
The SDA pin is at high impedance. See Figure 4.
edge, and data transfer sequence.
Figure 5. Byte Write Sequence
S
T
Signals From
The Master
A
R
Slave
Address
0
A
C
Word Address
Byte 1
Word Address
Byte 0
Data
S
T
O
P
T
SDA Bus
Signals From
The Slave
S 1010
P
A
C
A
C
A
C
K
K
K
K
Figure 6. Page Write Sequence
S
T
Signals From
The Master
A
R
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Data
S
T
O
P
T
SDA Bus
Signals From
The Slave
S 1 01 0
0
A
C
A
C
A
C
A
C
P
K
K
K
K
Characteristics subject to change without notice.
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