UPD4482183GF-A50 datasheet, PDF

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UPD4482183GF-A50: Description8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT; File Size286KB，28 Pages; ManufacturerNEC ( Renesas ); Websitehttps://www2.renesas.cn/zh-cn/

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UPD4482183GF-A50 Overview

8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD4482163, 4482183, 4482323, 4482363

8M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

DOUBLE CYCLE DESELECT

Description

The

PD4482163 is a 524,288-word by 16-bit, the

PD4482183 is a 524,288-word by 18-bit,

PD4482323 is a 262,144-

word by 32-bit and the

PD4482363 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS

technology using Full-CMOS six-transistor memory cell.

The

PD4482163,

PD4482183,

PD4482323 and

PD4482363 integrates unique synchronous peripheral circuitry, 2-

bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single

clock input (CLK).

The

PD4482163,

PD4482183,

PD4482323 and

PD4482363 are suitable for applications which require synchronous

operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In

the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.

The

PD4482163,

PD4482183,

PD4482323 and

PD4482363 are packaged in 100-pin PLASTIC LQFP with a 1.4

mm package thickness for high density and low capacitive loading.

Features

•

Single 3.3 V power supply

•

Synchronous operation

•

Operating temperature : T

= 0 to 70

°C

(-A44, -A50, -A60)

−40

+85 °C

(-A44Y, -A50Y, -A60Y)

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

Double-Cycle deselect timing

•

All registers triggered off positive clock edge

•

3.3 V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 to /BW4, /BWE (

PD4482323,

PD4482363)

/BW1, /BW2, /BWE (

PD4482163,

PD4482183)

Global write enable : /GW

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M14904EJ3V0DS00 (3rd edition)

Date Published December 2002 NS CP(K)

Printed in Japan

The mark shows major revised points.

The mark

shows major revised points.

2000

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