IBM043611ULAB4M x 1612/10, 3.3VMMDM15DSU-021045023.
Preliminary
Features
• 32K x 36 or 64K x 18 organizations
• 0.45 Micron CMOS technology
• Synchronous pipeline mode of operation with
self-timed late write
• Single Differential PECL Clock compatible with
LVTTL Levels
• Single +3.3V power supply and ground
• Common I/O & LVTTL I/O compatible
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
IBM043611ULAB
IBM041811ULAB
32K x 36 & 64K x 18 SRAM
• Registered outputs
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write capability & Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
The IBM043611ULAB and IBM041811ULAB 1Mb
SRAM
S
are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 4 ns
cycle times. Differential K clocks are used to initiate
the read/write operation and all internal operations
are self-timed. At the rising edge of the K clock, all
Addresses, Write-Enables, Sync Select, and Data
Ins are registered internally. Data Outs are updated
from output registers off the next rising edge of the K
clock. An internal Write buffer allows write data to
follow one cycle after addresses and controls. The
chip is operated with a single +3.3V power supply
and is compatible with LVTTL I/O interfaces.
77H9966.T1
11/98
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 23
IBM043611ULAB
IBM041811ULAB
32K x 36 & 64K x 18 SRAM
Preliminary
x36 BGA Pinout (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ23
DQ19
V
DDQ
DQ21
DQ26
V
DDQ
DQ27
DQ32
V
DDQ
DQ34
DQ30
NC
NC
V
DDQ
2
SA8
NC
SA9
DQ18
DQ24
DQ20
DQ25
DQ22
V
DD
DQ31
DQ28
DQ33
DQ29
DQ35
SA14
NC
TMS
3
SA7
NC
SA6
V
SS
V
SS
V
SS
SBWc
V
SS
NC
V
SS
SBWd
V
SS
V
SS
V
SS
M1*
SA13
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA1
SA0
V
DD
SA12
TCK
5
SA4
NC
SA5
V
SS
V
SS
V
SS
SBWb
V
SS
NC
V
SS
SBWa
V
SS
V
SS
V
SS
M2*
SA11
TDO
6
SA3
NC
SA2
DQ17
DQ11
DQ15
DQ10
DQ13
VDD
DQ4
DQ7
DQ2
DQ6
DQ0
SA10
NC
NC
7
V
DDQ
NC
NC
DQ12
DQ16
V
DDQ
DQ14
DQ9
V
DDQ
DQ8
DQ3
V
DDQ
DQ1
DQ5
NC
ZZ
V
DDQ
Note:
* M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to V
SS
and V
DD
, respec-
tively.
x18 BGA Pinout (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ9
NC
V
DDQ
NC
DQ12
V
DDQ
NC
DQ14
V
DDQ
DQ16
NC
NC
NC
V
DDQ
2
SA8
NC
SA9
NC
DQ10
NC
DQ11
NC
V
DD
DQ13
NC
DQ15
NC
DQ17
SA15
SA13
TMS
3
SA7
NC
SA6
V
SS
V
SS
V
SS
SBWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
M1
SA14
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA1
SA0
V
DD
NC
TCK
5
SA4
NC
SA5
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
SBWa
V
SS
V
SS
V
SS
M2
SA12
TDO
6
SA3
NC
SA2
DQ8
NC
DQ6
NC
DQ4
V
DD
NC
DQ2
NC
DQ1
NC
SA11
SA10
NC
7
V
DDQ
NC
NC
NC
DQ7
V
DDQ
DQ5
NC
V
DDQ
DQ3
NC
V
DDQ
NC
DQ0
NC
ZZ
V
DDQ
Note:
* M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to V
SS
and V
DD
, respec-
tively.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9966.T1
11/98
Page 2 of 23
Preliminary
IBM043611ULAB
IBM041811ULAB
32K x 36 & 64K x 18 SRAM
Pin Description
SA0-SA15
DQ0-DQ35
K, K
SW
SBWa
SBWb
SBWc
SBWd
Address Input
Data I/O
Differential PECL CLocks (LVTTL Compatible)
Write Enable, global
Write Enable, Byte a (DQ0 to DQ8)
Write Enable, Byte b (DQ9 to DQ17)
Write Enable, Byte c (DQ18 to DQ26)
Write Enable, Byte d (DQ27 to DQ35)
TDO
SS
M1, M2
V
DD
V
SS
V
DDQ
G
ZZ
NC
IEEE 1149 Test Output
Synchronous Select
Mode Inputs- Selects Read Protocol Operation.
Power Supply (+3.3V)
Ground
Output Power Supply
Asynchronous Output Enable
Asynchronous Sleep Mode
No Connect
TMS, TDI, TCK IEEE 1149 Test Inputs
Block Diagram
2:1 MUX
SA0-SA15
K
SS
ZZ
SW
SBW
RD Add
Register
Latch
WR Add
Register
Row Decode
32Kx36
or
64K x18
Array
Column Decode
Read/Write Amp
SW
Register
SW
Register
Latch
SBW
Register
SBW
Register
Match
2:1 MUX
Write
Buffer
Data Out
Register
SS
Register
SS
Register
G
DQ0-DQ35
77H9966.T1
11/98
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 23
IBM043611ULAB
IBM041811ULAB
32K x 36 & 64K x 18 SRAM
Preliminary
SRAM Features
Late Write
Late Write function allows for write data to be registered one cycle after addresses and controls. This feature
eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is
accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. If a read cycle occurs after a write cycle, the address and write data information are stored temporarily
in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be updated with
the address and data from the holding registers. Read cycle addresses are monitored to determine if read
data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array data occurs
on a byte-by-byte basis. When one byte is written during a write cycle, read data from the last written address
will have new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. The SRAM
supports the following protocols:
• Single Clock, Flow-Through (M1 = V
SS
, M2 = V
SS
)
• Pipeline (M1 = V
SS
, M2 = V
DD
)
• Register-Latch (M1 = V
DD
, M2 = V
SS
)
This datasheet only describes Pipeline functionality. Mode control inputs must be set with power-up and must
not change during SRAM operation.
Sleep Mode
Sleep Mode is accomplished by switching asynchronous signal ZZ high. When the SRAM is in Sleep Mode,
the outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved
and a recovery time (t
ZZR
) is required before the SRAM resumes normal operation.
Power-Up Requirements
In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up
time after V
DD
reaches its operating range.
Power-Up/ Power-Down Sequencing
The Power supplies need to be powered up in the following manner: V
DD
, V
DDQ
, and Inputs. The power-down
sequencing must be the reverse. V
DDQ
must never be allowed to exceed V
DD
.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
77H9966.T1
11/98
Page 4 of 23
Preliminary
IBM043611ULAB
IBM041811ULAB
32K x 36 & 64K x 18 SRAM
Ordering Information
Part Number
IBM041811ULAB - 5
64K x 18
IBM041811ULAB - 6
IBM043611ULAB - 5
32K x 36
IBM043611ULAB - 6
3.0ns Access / 6ns Cycle
3.0ns Access / 6ns Cycle
7 x 17 BGA
2.5ns Access / 5ns Cycle
Organization
Speed
2.5ns Access / 5ns Cycle
Leads
77H9966.T1
11/98
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 23
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