UPD4481362 datasheet, PDF - EEWORLD Datasheet

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UPD4481362: Description8M-BIT ZEROSB SRAM PIPELINED OPERATION; File Size342KB，28 Pages; ManufacturerNEC ( Renesas ); Websitehttps://www2.renesas.cn/zh-cn/

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UPD4481362 Overview

8M-BIT ZEROSB SRAM PIPELINED OPERATION

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD4481162, 4481182, 4481322, 4481362

8M-BIT ZEROSB

SRAM

PIPELINED OPERATION

Description

The

PD4481162 is a 524,288-word by 16-bit, the

PD4481182 is a 524,288-word by 18-bit, the

PD4481322 is a

262,144-word by 32-bit and the

PD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD4481162,

PD4481182,

PD4481322 and

PD4481362 are optimized to eliminate dead cycles for read to

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The

PD4481162,

PD4481182,

PD4481322 and

PD4481362 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).

In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal

operation.

The

PD4481162,

PD4481182,

PD4481322 and

PD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4

mm package thickness for high density and low capacitive loading.

Features

•

Low voltage core supply : V

= 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y)

= 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y)

•

Synchronous operation

•

Operating temperature : T

= 0 to 70

°C

(-A44, -A50, -A60, -A75, -C60, -C75)

−40

+85 °C

(-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y)

•

100 percent bus utilization

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

All registers triggered off positive clock edge

•

3.3V or 2.5V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 to /BW4 (

PD4481322 and

PD4481362)

/BW1 and /BW2 (

PD4481162 and

PD4481182)

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M15562EJ3V0DS00 (3rd edition)

Date Published December 2002 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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