HY27SA161G1M-FIS datasheet, PDF

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HY27SA161G1M-FIS: DescriptionFlash, 64MX16, 12000ns, PBGA63, 8.50 X 15 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63; Categorystorage storage; File Size668KB，45 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY27SA161G1M-FIS Overview

Flash, 64MX16, 12000ns, PBGA63, 8.50 X 15 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, FBGA-63

HY27SA161G1M-FIS Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	BGA
package instruction	TFBGA, BGA63,8X12,32
Contacts	63
Reach Compliance Code	compliant
ECCN code	3A991.B.1.A
Maximum access time	12000 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
length	15 mm
memory density	1073741824 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	8K
Number of terminals	63
word count	67108864 words
character code	64000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA63,8X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
page size	256 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Programming voltage	1.8 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	8K
Maximum standby current	0.0001 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	SLC NAND TYPE
width	8.5 mm

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Preliminary

HY27UA(08/16)1G1M Series

HY27SA(08/16)1G1M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

Document Title

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory

Revision History

No.

0.0

0.1

1) Initial Draft

1) Add 1.8V Operation Product to Data sheet

1) Change AC Characteristics

0.2

- tWP(25ns->40ns), tWC(50ns->60ns),

- tRP(30ns->40ns), tRC(50ns->60ns),

- tREADID(35ns->45ns)

1) Add Errata (3V Product)

tWH

Specification

Relaxed value

0.3

2) Add Applicaiton Note

Reset command must be issued when the controller writes data to

another 512Mb.(i.e. When A26 is changed during program.)

3) Modify the description of Device Operations

- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled

(Enabled) (Page23)

4) Add the description of System Interface Using /CE don’t care (Page40)

tREH

May. 14. 2004

Preliminary

Apr. 29. 2004

Preliminary

History

Draft Date

Nov. 28. 2003

Mar. 11. 2004

Remark

Preliminary

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 0.3 / May. 2004

Preliminary

HY27UA(08/16)1G1M Series

HY27SA(08/16)1G1M Series

1Gbit (128Mx8bit / 64Mx16bit) NAND Flash

DESCRIPTION

The HYNIX HY27(U/S)A(08/16)1G1M series is a family of non-volatile Flash memories that use NAND cell technology.

The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264

Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus.

This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is

strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hard-

ware protection against program and erase operations.

The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER)

Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to

be connected to a single pull-up resistor.

A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation

fails, the data can be programmed in another page without having to resend the data to be programmed.

Each device has a Cache Program feature which improves the program throughput for large files. It loads the data in a

Cache Register while the previous data is transferred to the Page Buffer and programmed into the memory array.

The devices are available in the following packages:

48-TSOP1

(12 x 20 x 1.2 mm)

- 48-WSOP1

(12 x 17 x 0.7 mm)

- 63-FBGA

(8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch)

Three options are available for the NAND Flash family:

- Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download the boot code from

page 0.

- Chip Enable Dont Care, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions

during the latency time do not stop the read operation.

- A Serial Number, which allows each device to be uniquely identified. The Serial Number options is subject to an NDA

(Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your near-

est HYNIX Sales office.

Devices are shipped from the factory with Block 0 always valid and the memory content bits, in valid blocks, erased to

'1'.

Rev 0.3 / May. 2004

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