21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with Dual Outputs
and 3-State Outputs
Product Features
PI74ALVCH16820 is designed for low-voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce) < 0.8V
at V
CC
= 3.3V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot) < 2.0V
at V
CC
= 3.3V, T
A
= 25°C
Bus Hold retains last active bus state during 3-state
eliminating the need for external pullup resistors
Industrial operation: 40°C to +85°C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced using the Companys advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16820, a 10-bit flip-flop designed for 2.3V to 3.3V
V
CC
operation, features edge-triggered D-type flip-flops. On the
positive transition of clock (CLK) input, the device provides true
data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In high-impedance state, outputs neither load nor
drive the bus lines significantly. The high-impedance state and
increased drive are able to drive bus lines without interface or pullup
components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor whose
minimum value is determined by the current sinking capability of the
driver.
To prevent floating inputs and to eliminate the need for pullup/
down resistors, the PI74ALVCH16820 has Bus Hold which retains
the data inputs last state whenever the data input goes to high-
impedance .
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
OE
1
2
OE
28
2
C
1
1
D
CLK
56
55
1
Q
1
D
1
3
1
Q
2
TO 9 OTHER CHANNELS
1
PS8126A
05/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with
Dual and 3-State Outputs
Product Pin Description
Pin Name
OE
CLK
Dx
Qx
GND
V
CC
D e s cription
O utput Enable Input (Active LO W)
Clock Input (Active HIGH)
Data Inputs
3- State O utputs
Ground
Power
Maximum Ratings
(Above which the useful life may be impaired.
For user guidelines, not tested.)
Storage Temperature .................................... 65°C to +150°C
Ambient Temperature with Power Applied ... 40°C to +85°C
Input Voltage Range, V
IN ..................................
0.5V to V
CC
+0.5V
Output Voltage Range, V
OUT ..........................
0.5V to V
CC
+0.5V
DC Input Voltage ............................................. 0.5V to +5.0V
DC Output Current ...................................................... 100mA
Power Dissipation ........................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Truth Table
(1)
Inputs
OEn
L
L
L
H
CLK
L
X
D
H
L
X
X
Outputs
Qn
H
L
Q
0
Z
Note:
1. H
L
X
Z
↑
n
Product Pin Configuration
1OE
1Q1
1Q2
GND
2Q1
2Q2
V
CC
3Q1
3Q2
4Q1
GND
4Q2
5Q1
5Q2
6Q1
6Q2
7Q1
GND
7Q2
8Q1
8Q2
V
CC
9Q1
9Q2
GND
10Q1
10Q2
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLK
D1
NC
GND
D2
NC
V
CC
D3
NC
D4
GND
NC
D5
NC
D6
NC
D7
GND
NC
D8
NC
V
CC
D9
NC
GND
D10
NC
NC
=
=
=
=
=
=
High Signal Level
Low Signal Level
Irrelevant
High Impedance
LOW-to-HIGH Transition
1,2
56-Pin
A, V
2
PS8126A
05/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with
Dual and 3-State Outputs
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 3.3V ± 10%)
Parame te rs De s cription
V
CC
V
IH(3)
V
IL(3)
V
IN(3)
V
OUT(3)
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Voltage
Output Voltage
I
OH
= 100
µ
A, V
CC
= Min. to Max.
Output
HIGH
Voltage
V
IH
= 1.7V, I
OH
= 6mA, V
CC
= 2.3V
V
IH
= 1.7V, I
OH
= 12mA, V
CC
= 2.3V
V
IH
= 2.0V, I
OH
= 12mA, V
CC
= 2.7V
V
IH
= 2.0V, I
OH
= 12mA, V
CC
= 3.0V
V
IH
= 2.0V, I
OH
= 24mA, V
CC
= 3.0V
I
OL
= 100
µ
A, V
IL
= Min. to Max.
V
OL
Output
LOW
Voltage
V
IL
= 0.7V, I
OL
= 6mA, V
CC
= 2.3V
V
IL
= 0.7V, I
OL
= 12mA, V
CC
= 2.3V
V
IL
= 0.8V, I
OL
= 12mA, V
CC
= 2.7V
V
IL
= 0.8V, I
OL
= 24mA, V
CC
= 3.0V
I
OH(3)
Output
HIGH
Current
Output
LOW
Current
Input Current
Input
Hold
Current
Output Current
(3- State Outputs)
Supply Current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
IN
= V
CC
or GND, V
CC
= 3.6V
V
IN
= 0.7V, V
CC
= 2.3V
V
IN
= 1.7V, V
CC
= 2.3V
V
IN
= 0.8V, V
CC
= 3.0V
V
IN
= 2.0V, V
CC
= 3.0V
V
IN
= 0 to 3.6V, V
CC
= 3.6V
I
OZ
I
CC
∆I
CC
C
I
C
O
V
OUT
= V
CC
or GND, V
CC
= 3.6V
V
CC
= 3.6V, I
OUT
= 0
µA,
V
IN
= GND or V
CC
I
IN (HOLD)
45
45
75
75
±500
±10
40
750
3.5
6
7
pF
µA
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
0
0
V
CC
- 0.2
2.0
1.7
2.2
2.4
2.0
0.2
0.4
0.7
0.4
0.55
12
12
24
12
24
24
±5
mA
V
Te s t Conditions
(1)
M in.
2.3
1.7
2.0
0.7
0.8
V
CC
V
CC
Typ.
(2)
M ax.
3.6
Units
V
OH
I
OL(3)
I
IN
Supply Current per V
CC
= 3.0V to 3.6V
Input @ TTL HIGH One Input at V
CC
- 0.6V
Other Inputs at V
CC
or GND
Control Inputs
Data Inputs
Outputs
V
IN
= V
CC
or GND, V
CC
= 3.3V
V
O
= V
CC
or GND, V
CC
= 3.3V
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
3
PS8126A
05/07/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16820
3.3V 10-Bit Flip-Flop with
Dual and 3-State Outputs
Timing Requirements over Operating Range
PI74ALVCH16820
Parame te rs
f
CLOCK
t
W
t
SU
t
H
∆
t
/∆
v(3)
De s cription
Clock Frequency
Pulse duration CLK high or low
Setup time data before CLK
↑
Hold time data after CLK
↑
Input Transition Rise or Fall
V
CC
= 2.5 V ±0.2 V
M in.
0
3.3
1.7
1.1
M ax.
150
V
CC
= 2.7 V
M in.
0
3.3
1.8
1.1
M ax.
150
V
CC
= 3.3 V ±0.3 V
M in.
0
3.3
1.4
1.0
0
10
ns/V
M ax.
150
MHz
ns
Units
Switching Characteristics over Operating Range
(1)
Parame te rs
From
(Input)
CLK
OE
OE
To
(Output)
Q
Q
Q
V
CC
= 2.5V ± 0.2V
M in.
(2)
150
1.0
1.0
1.3
6.5
6.9
5.9
M ax.
V
CC
= 2.7V
M in.
(2)
150
5.5
6.1
5.0
M ax.
V
CC
= 3.3V ± 0.3V
M in.
(2)
150
1.0
1.0
1.0
4.8
5.0
4.5
M ax.
Units
MHz
ns
ns
ns
f
MAX
t
PD
t
EN
t
DIS
Notes:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Recommended operating condition.
Operating Characteristics,
T
A
= 25°C
Parame te rs
C
PD
Power Dissipation
Capacitance
O utputs Enabled
O utputs Disabled
Te s t Conditions
V
CC
= 2.5V ±0.2V
Typical
60
38
V
CC
= 3.3V ±0.3V
Typical
63
46
Units
C
L
= 50pF, f = 10 MHz
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
4
PS8126A
05/07/01
京公网安备 11010802033920号
EEWORLD
