K7A803600B
K7A801800B
256Kx36 & 512Kx18 Synchronous SRAM
8Mb Sync. Pipelined Burst SRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 5.0 April 2006
K7A803600B
K7A801800B
Document Title
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
History
Initial draft
1. Delete pass- through
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB2
form 50mA to 60mA
Change ordering information( remove 225MHz at SPB)
1. Delete 119BGA package
1. Remove x32 organization
1. Add the overshoot timing
1. Add Pb-free package
Draft Date
May. 18 . 2001
June. 26. 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
2.0
2.1
3.0
4.0
5.0
April. 01. 2002
April. 04. 2003
Nov. 17. 2003
Feb. 16. 2006
Apr. 03. 2006
Final
Final
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
Rev. 5.0 April 2006
K7A803600B
K7A801800B
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A803600B and K7A801800B are 9,437,184-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system¢s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A803600B and K7A801800B are fabricated using
SAMSUNG¢s high performance CMOS technology and is
available in a 100pin TQFP and Multiple power and ground
pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-16
6.0
3.5
3.5
-14
7.2
3.8
3.8
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
256Kx36 , 512Kx18
MEMORY
ARRAY
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A′
0
~A′
1
ADSP
A
0
~A
17
or A
0
~A
18
ADDRESS
REGISTER
A
2
~A
17
or A
2
~A
18
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQP
a
,DQP
b
DQPa ~ DQPd
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Rev. 5.0 April 2006
MCU
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