K7A803600B
K7A803200B
K7A801800B
Document Title
256Kx36/x32 & 512Kx18 Synchronous SRAM
256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
History
Initial draft
1. Delete pass- through
1. Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB2
form 50mA to 60mA
Draft Date
May. 18 . 2001
June. 26. 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
256Kx36/x32 & 512Kx18 Synchronous SRAM
256Kx36 & 256Kx32 & 512Kx18-bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A803600B, K7A803200B and K7A801800B are
9,437,184-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 256K(512K) words of 36/32(18) bits and
integrates address and control registers, a 2-bit burst
address counter and added some new functions for high
performance cache RAM applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system¢s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A803600B, K7A803200B and K7A801800B are fab-
ricated using SAMSUNG¢s high performance CMOS tech-
nology and is available in a 100pin TQFP and 119BGA
package (100pin TQFP only for K7A803200B).
Multiple power and ground pins are utilized to minimize
ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-16
6.0
3.5
3.5
-14
7.2
3.8
3.8
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
17
or A
0
~A
18
ADDRESS
REGISTER
A
2
~A
17
or A
2
~A
18
A′
0
~A′
1
256Kx36/32 , 512Kx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQP
a
,DQP
b
DQPa ~ DQPd
-3-
Nov 2001
Rev 1.0
K7A803600B
K7A803200B
K7A801800B
PIN CONFIGURATION
(TOP VIEW)
256Kx36/x32 & 512Kx18 Synchronous SRAM
ADSC
ADSP
WEb
WEa
ADV
83
N.C.
N.C.
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
18
A
11
A
12
A
13
A
14
A
15
A
16
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,43
44,45,46,47,48,49,50
80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
SYMBOL
V
DD
V
SS
N.C.
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
TQFP PIN NO.
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,51,52,53,56,
57,66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
LBO
V
SS
DQa
0
~ a
7
DQb
0
~ b
7
DQPa, Pb
V
DDQ
V
SSQ
Data Inputs/Outputs
Output Power Supply
(2.5V or 3.3V)
Output Ground
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
-5-
A
17
50
N.C.
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
N.C.
DQb
0
DQb
1
V
SSQ
V
DDQ
DQb
2
DQb
3
N.C.
V
DD
N.C.
V
SS
DQb
4
DQb
5
V
DDQ
V
SSQ
DQb
6
DQb
7
DQPb
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7A801800B(512Kx18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
N.C.
N.C.
V
DDQ
V
SSQ
N.C.
DQPa
DQa
7
DQa
6
V
SSQ
V
DDQ
DQa
5
DQa
4
V
SS
N.C.
V
DD
ZZ
DQa
3
DQa
2
V
DDQ
V
SSQ
DQa
1
DQa
0
N.C.
N.C.
V
SSQ
V
DDQ
N.C.
N.C.
N.C.
Nov 2001
Rev 1.0
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