PSMN1R1-30EL
2 April 2014
I2P
AK
N-channel 30 V 1.3 mΩ logic level MOSFET in I2PAK
Product data sheet
1. General description
Logic level N-channel MOSFET in I2PAK package qualified to 175 °C. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
2. Features and benefits
•
•
High efficiency due to low switching and conduction losses
Suitable for logic level gate drive sources
3. Applications
•
•
•
•
DC-to-DC converters
Load switiching
Motor control
Server power supplies
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
T
mb
= 25 °C; V
GS
= 10 V;
Fig. 2
T
mb
= 25 °C;
Fig. 1
[1]
Min
-
-
-
-55
Typ
-
-
-
-
Max
30
120
338
175
Unit
V
A
W
°C
Static characteristics
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
V
GS
= 10 V; I
D
= 25 A; T
j
= 100 °C;
Fig. 13
Dynamic characteristics
Q
GD
Q
G(tot)
gate-drain charge
total gate charge
V
GS
= 4.5 V; I
D
= 75 A; V
DS
= 15 V;
Fig. 14; Fig. 15
-
-
37
118
-
-
nC
nC
-
1.5
1.8
mΩ
[2]
-
1.1
1.3
mΩ
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NXP Semiconductors
PSMN1R1-30EL
N-channel 30 V 1.3 mΩ logic level MOSFET in I2PAK
Symbol
E
DS(AL)S
Parameter
non-repetitive drain-
source avalanche
energy
[1]
[2]
Conditions
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 120 A;
V
sup
≤ 30 V; R
GS
= 50 Ω; unclamped
Min
-
Typ
-
Max
1.9
Unit
J
Avalanche ruggedness
Continuous current is limited by package.
Measured 3 mm from package.
5. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to
drain
1 2 3
Simplified outline
mb
Graphic symbol
D
G
mbb076
S
I2PAK (SOT226)
6. Ordering information
Table 3.
Ordering information
Package
Name
PSMN1R1-30EL
I2PAK
Description
plastic single-ended package (I2PAK); TO-262
Version
SOT226
Type number
7. Marking
Table 4.
Marking codes
Marking code
PSMN1R1-30EL
Type number
PSMN1R1-30EL
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
PSMN1R1-30EL
Parameter
drain-source voltage
drain-gate voltage
Conditions
T
j
≥ 25 °C; T
j
≤ 175 °C
T
j
≥ 25 °C; T
j
≤ 175 °C; R
GS
= 20 kΩ
All information provided in this document is subject to legal disclaimers.
Min
-
-
Max
30
30
Unit
V
V
2 / 13
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
2 April 2014
NXP Semiconductors
PSMN1R1-30EL
N-channel 30 V 1.3 mΩ logic level MOSFET in I2PAK
Symbol
V
GS
P
tot
I
D
Parameter
gate-source voltage
total power dissipation
drain current
Conditions
T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 2
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 2
[1]
[1]
Min
-20
-
-
-
-
-55
-55
-
Max
20
338
120
120
1609
175
175
260
Unit
V
W
A
A
A
°C
°C
°C
I
DM
T
stg
T
j
T
sld(M)
I
S
I
SM
E
DS(AL)S
peak drain current
storage temperature
junction temperature
peak soldering temperature
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 3
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 120 A;
V
sup
≤ 30 V; R
GS
= 50 Ω; unclamped
[1]
-
-
120
1609
A
A
Avalanche ruggedness
non-repetitive drain-source
avalanche energy
[1]
120
P
der
(%)
80
-
1.9
J
Continuous current is limited by package.
03aa16
5 00
I
D
(A)
4 00
003a a f774
3 00
40
2 00
(1)
1 00
0
0
50
100
150
T
mb
(°C)
200
0
0
50
10 0
150
200
T
mb
( C)
Fig. 1.
Normalized total power dissipation as a
function of mounting base temperature
Fig. 2.
Continuous drain current as a function of
mounting base temperature.
PSMN1R1-30EL
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
2 April 2014
3 / 13
NXP Semiconductors
PSMN1R1-30EL
N-channel 30 V 1.3 mΩ logic level MOSFET in I2PAK
I
D
(A)
10
4
003a a f773
10
3
Limit R
DS on
= V
DS
/ I
D
10
2
DC
t
p
=10
ms
100
ms
1 ms
10
10 ms
100 ms
1
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9. Thermal characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
thermal resistance
from junction to
ambient
1
Z
th(j-mb)
(K/W)
10
-1
δ
= 0.5
Conditions
Fig. 4
Min
-
Typ
0.22
Max
0.44
Unit
K/W
R
th(j-a)
Vertical in free air
-
60
-
K/W
003aaf772
0.2
0.1
0.05
10
-2
0.02
P
δ=
T
tp
single shot
10
-3
tp
t
T
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig. 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration; typical
values
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved
PSMN1R1-30EL
Product data sheet
2 April 2014
4 / 13
NXP Semiconductors
PSMN1R1-30EL
N-channel 30 V 1.3 mΩ logic level MOSFET in I2PAK
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 10; Fig. 11
I
D
= 2 mA; V
DS
= V
GS
; T
j
= 175 °C;
Fig. 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 11
I
DSS
drain leakage current
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 175 °C
I
GSS
gate leakage current
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
Fig. 12
V
GS
= 10 V; I
D
= 25 A; T
j
= 175 °C;
Fig. 13; Fig. 12
V
GS
= 10 V; I
D
= 25 A; T
j
= 100 °C;
Fig. 13
R
G
Q
G(tot)
gate resistance
f = 1 MHz
-
1.1
-
Ω
-
1.5
1.8
mΩ
-
2.1
2.5
mΩ
-
1.2
1.6
mΩ
[1]
Min
30
27
1.3
0.5
-
-
-
-
-
-
Typ
-
-
1.7
-
-
0.02
250
10
10
1.1
Max
-
-
2.15
-
2.5
10
500
100
100
1.3
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
Static characteristics
V
GS(th)
Dynamic characteristics
total gate charge
I
D
= 75 A; V
DS
= 15 V; V
GS
= 10 V;
Fig. 14; Fig. 15
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V;
Fig. 14; Fig. 15
I
D
= 75 A; V
DS
= 15 V; V
GS
= 4.5 V;
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
PSMN1R1-30EL
-
-
-
-
-
-
-
243
222
118
39
22
17
37
2.8
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
nC
V
gate-source charge
pre-threshold gate-
source charge
post-threshold gate-
source charge
gate-drain charge
gate-source plateau
voltage
Fig. 14; Fig. 15
V
DS
= 15 V;
Fig. 14; Fig. 15
All information provided in this document is subject to legal disclaimers.
-
© NXP Semiconductors N.V. 2014. All rights reserved
Product data sheet
2 April 2014
5 / 13
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