Preliminary Specification
P1727/66
Low Power Notebook LCD Panel EMI Reduction IC
FEATURES
•
•
•
FCC approved method of EMI attenuation
Generates a low EMI spread spectrum of
the input clock frequency
Optimized for frequency range:
P1727X: 20MHz to 40MHz
P1766X: 40MHz to 80MHz
Internal loop filter minimizes external
components and board space
8 different frequency deviations ranging
from
+/-0.625% to –3.50%
•
•
•
•
Low inherent cycle-to-cycle jitter
3.3V operating voltage
CMOS/TTL compatible inputs and outputs
Ultra low power
CMOS design
TBD mA @3.3V, 54 MHz
TBD mA @3.3V, 65 MHz
•
•
•
•
•
Supports notebook VGA and other LCD
timing controller applications
Available in 8 pin SOIC and TSSOP
Qualified for Industrial Temp Spec. (+85C)
PRODUCT DESCRIPTION
The P1727/66 is a versatile spread spectrum
frequency modulator designed specifically for a
wide range of clock frequencies. The P1727/66
reduces electromagnetic interference (EMI) at
the clock source, allowing system wide
reduction of EMI of down stream (clock and
data dependent signals). The P1727/66 allows
significant system cost savings by reducing the
number of circuit board layers and shielding that
are traditionally required to pass EMI
regulations.
The P1727/66 modulates the output of a single
PLL in order to “spread” the bandwidth of a
synthesized clock, thereby decreasing the peak
amplitudes of its harmonics. This results in
significantly lower system EMI compared to the
typical narrow band signal produced by
oscillators and most clock generators. Lowering
EMI by increasing a signal’s bandwidth is called
“spread spectrum clock generation”.
The P1727/66 uses the most efficient and
optimized modulation profile approved by the
FCC and is implemented by using a proprietary
all-digital method.
APPLICATIONS
The P1727/66 is targeted towards notebook
LCD displays, other displays using an LVDS
interface, PC peripheral devices, and embedded
systems.
Figure 1 – P1727/66 Pin Diagram
CLKIN
VDD
VSS
ModOUT
1
2
3
4
P1727X
P1766X
8
7
6
5
PD#
NC
NC
REF
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
1of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
Figure 2 – P1727/66 Block Diagram
PD#
VDD
M o d u la tio n
C L K IN
F re q u e n c y
D iv id e r
F e ed b a ck
D iv id e r
PLL
Phase
D e te c to r
Loop
F ilte r
VCO
O u tp u t
D iv id e r
M odO UT
REF
P 1 7 2 7 /6 6 B lo c k D ia g r a m
VSS
Table 1-Power Down Selection
PD#
0
1
Spread Spectrum
N/A
ON
ModOut
Disabled
Normal
PLL
Disabled
Normal
Mode
Power Down
Normal
Table 2 Frequency Deviation Selection
P/N
P1727/66A
P1727/66B
P1727/66C
P1727/66D
Deviation
-1.25%
-1,75%
-2.50%
-3.50%
P/N
P1727/66E
P1727/66F
P1727/66G
P1727/66H
Deviation
+/-0.625%
+/-0.875%
+/-1.25%
+/-1.75%
PIN DESCRIPTION
PIN # Name
1
CLKIN
2
VDD
3
VSS
4
ModOut
5
REF
6
N/C
7
N/C
8
PD#
Type
I
P
P
O
I
N/C
N/C
I
Description
Connect to externally generated clock signal.
Connect to +3.3V
Ground Connection. Connect to system ground.
Spread Spectrum Clock Output.
Reference output.
No connect
No connect
Pull low to enable Power Down Mode. This pin has an internal pull-up
resistor.
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
2 of 6
http://www.pulsecore.com
Preliminary Specification
P1727/66
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
, V
IN
T
STG
T
A
Parameter
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Rating
-0.5 to +7.0
-65 to +125
0 to +70
Unit
V
ºC
ºC
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Parameter
Input Low Voltage
Input High Voltage
Input Low Current (100 KΩ input pull-up
resistor on inputs SR0, 1)
Input High Current (100 KΩ input pull-
down resistor on input SSON)
XOUT Output Low Current
(@ 0.4V, V
DD
= 3.3V)
XOUT Output High Current
(@ 2.5V, V
DD
= 3.3V)
Output Low Voltage
(V
DD
=3.3V, I
OL
= 20 mA)
Output High Voltage
(V
DD
=3.3V, I
OH
= 20 mA)
Static Supply Current
Standby Mode
Dynamic Supply Current
Normal Mode (3.3V and 10 pF loading)
Operating Voltage
Power Up Time
(First locked clock cycle after power up)
Clock Output Impedance
Min
GND – 0.3
2.0
-
-
-
-
-
2.5
-
TBD
f
IN-min
TBD
-
-
Typ
-
-
-
-
3
3
-
-
TBD
TBD
f
IN-typ
3.3
0.18
50
Max
0.8
V
DD
+ 0.3
-35
35
-
-
0.4
-
-
TBD
f
IN-max
TBD
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
AC ELECTRICAL CHARACTERISTICS
Symbol
f
IN
t
LH
Note 1
t
HL
Note 1
t
JC
t
D
Parameter
Input Frequency: P1727-X
P1766-X
Output Rise Time
(measured at 0.8V to 2.0V)
Output Fall Time
(measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output Duty Cycle
Min
20
40
0.7
0.6
-
45
Typ
-
0.9
0.8
-
50
Max
40
80
1.1
1.0
TBD
55
Unit
MHz
ns
ns
ps
%
Note1: t
LH
and t
HL
are measured into a capacitive load of 15pF
Oct., 2002
Revision B
3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054
Tel (408) 748-6988 • Fax (408) 748-0009
4 of 6
http://www.pulsecore.com
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