APA3160
20W Stereo Digital Class-D Audio Power Amplifier with EQ and DRC
Features
General Description
The APA3160 is a digital input, stereo, high efficiency,
Class-D audio amplifier available in a TQFP7x7-48P
package.
The APA3160 accepts the digital serial audio data and
using the digital audio processor to convert the audio
data becomes the stereo Class-D output speaker
amplifier. This provides the seamless integration between
the codec and the speaker amplifier.
The APA3160 is a slave device receiving clocks from ex-
ternal source, and the Class-D’ PWM switching fre-
s
quency is 352.8kHz for the sampling rate 44.1kHz or 384
kHz for sampling 48kHz, depend on the input signal’
s
sampling rate.
•
•
•
•
•
•
•
•
Operating Voltage: 8.0V~24V for PVDD
– 3.0V~3.6V for DVDD and AVDD
High Efficiency Class-D Operation Eliminate the
Need of Heatsinks
Digital Serial Audio Input (Stereo Output)
I
2
C Control Interface
Sampling Rate can Support from 32kHz to 192kHz
Separated Volume Control from 24dB to Mute
Soft Mute (50% Duty Cycle)
Programmable Dynamic Range Compression
– Power Limiter
– Speaker Protection
– Night-Mode Listening
Programmable Biquads for Speaker EQ
Shutdown and Mute Function
Thermal and Over-Current Protections with Auto-
Recovery
Space Saving Package TQFP7x7-48P
Lead Free and Green Devices Available
(RoHS Compliant)
•
•
•
•
Pin Configuration
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BBS
CBS
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
48
47
46
45
44
43
42
41
40
39
38
37
•
Applications
•
LCD TV
Simplified Application Circuit
OUT_A
OUT_A
PVDD_A
PVDD_A
ABS
GDREG
NC
TM1
TM2
AVSS
PLL_LF
AVSS
2V5_AV
1
2
3
4
5
6
7
8
9
10
11
12
APA3160
36
35
34
33
32
31
30
29
28
27
26
25
OUT_D
PVDD_D
PVDD_D
DBS
GDREG
DVREG
AGND
GND
DVSS
DVDD
TP3
RST
OUT_B
APA3160
OUT_C
IC
Control
2
SDA
SCL
OUT_D
Right
Channel
Speaker
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
1
www.anpec.com.tw
AVDD
ERROR
MCLK
TP1
TP2
2V5_DV
SD
LRCLK
SCLK
SDIN
SDA
SCL
Digital Audio
Source
MCLK
LRCLK
SCLK
SDIN
Left
Channel
Speaker
13
14
15
16
17
18
19
20
21
22
23
24
TQFP7x7-48P
(TOP VIEW)
APA3160
Ordering and Marking Information
APA3160
Assembly Material
Handling Code
Temperature Range
Package Code
Package Code
QCA : TQFP7x7-48P
Operating Ambient Temperature Range
I : -40 to 85
o
C
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
XXXXX - Date Code
APA3160 QCA :
APA3160
XXXXX
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
Supply Voltage (PVDD_X to PGND_XX)
Supply Voltage (DVDD to DVSS)
Supply Voltage (AVDD to AVSS)
Input Voltage (MCLK to AVSS)
(Note 1)
Rating
-0.3 to 26
-0.3 to 3.6
-0.3 to 3.6
-0.5 to AVDD+2.5
-0.5 to DVDD+2.5
-0.3 to +32
-0.3 to +43
-0.3 to +0.3
150
-65 to +150
260
Internally Limited
ο
Parameter
Unit
Input Voltage (SD, RST, LRCLK, SCLK, SDIN, SDA, SCL to DVSS)
Input Voltage (OUT_X to PGND_XX)
Input Voltage (XBS to PGND_XX)
Input Voltage (AVSS, DVSS, AGND to PGND_XX)
T
J
T
STG
T
SDR
P
D
Maximum Junction Temperature
Storage Temperature Range
Soldering Temperature Range, 10 seconds
Power Dissipation
V
C
C
ο
ο
C
W
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
θ
JA
θ
JC
Parameter
Junction-to-Ambient Resistance in Free Air
(Note 2)
TQFP7x7-48P
Junction-to-Case Resistance in Free Air
(Note 3)
TQFP7x7-48P
Typical Value
25
-
Unit
°C/W
°C/W
Note 2:
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFP7X7-48P is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TQFP7X7-48P package.
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
2
www.anpec.com.tw
APA3160
Recommended Operating Conditions
Symbol
V
DD
PV
DD
V
IH
V
IL
T
A
T
J
R
L
L
O
Supply Voltage
Full Bridge Stage Supply Voltage (PVDD_X)
High Level Threshold Voltage
Low Level Threshold Voltage
Ambient Temperature Range
Junction Temperature Range
Speaker Resistance
Output Low Pass Filter Inductance
SD, MCLK, LRCLK, SCLK, SDIN,
SDA, SCL, RST
SD, MCLK, LRCLK, SCLK, SDIN,
SDA, SCL, RST
Parameter
Range
Min.
3
8
2
0
-40
-40
6
10
Max.
3.6
24
5
1
85
125
-
-
ο
Unit
V
C
Ω
µH
PWM Operating Conditions
Symbol
Parameter
Test Conditions
32 kHz Data Rate ±2%
f
S
Output Sample Rate
44.1k/88.2k/176.4 kHz Data Rate ±2%
48k/96k/192 kHz Data Rate ±2%
Value
256
352.8
384
kHz
Unit
PLL Input Parameters and External Filter Components
Symbol
f
MCLK
Parameter
MCLK Frequency
MCLK Duty Cycle
tr/tf
(MCLK)
Rise/Fall Time for MCLK
LRCLK Allowable Drift before
LRCLK Reset
External PLL Filter Capacitor C1
External PLL Filter Capacitor C2
External PLL Filter Resistor R
SMD 0603 Y5V
SMD 0603 Y5V
Test Conditions
APA3160
Min.
2.8224
40
-
-
-
-
-
Typ.
-
50
-
-
47
4.7
470
Max.
24.576
60
5
4
-
-
-
Unit
MHz
%
ns
MCLKs
nF
Ω
Electrical Characteristics
T
A
=25 C, PV
DD
=18V, V
DD
=3.3V (AVDD and DVDD), R
L
=8Ω, BD Mode, f
S
=48kHz (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
DC CHARACTERISTICS
I
DD
3.3V Supply Current (AVDD,
DVDD)
Full Bridge Stage Supply
Current
(PVDD_X)
Low Level Input Current
Normal Mode (No load)
Reset (No load)
Normal Mode (No load)
Reset (No load)
V
I
<V
IL
, V
DD
=3.6V (AVDD and
DVDD)
3
ο
APA3160
Typ.
Max.
Unit
-
-
-
-
-
10
7.2
18
0.5
150
20
14.5
36
1
-
µA
mA
I
PVDD
I
IL
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
www.anpec.com.tw
APA3160
Electrical Characteristics (Cont.)
T
A
=25 C, PV
DD
=18V, V
DD
=3.3V (AVDD and DVDD), R
L
=8Ω, BD Mode, f
S
=48kHz (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
DC CHARACTERISTICS (CONT.)
I
IH
High Level Input Current
Thermal Protection Threshold
T
TP
η
R
OUT
Thermal Protection Threshold
Hysteresis
Efficiency
Internal Pull-Down Resistance at
Each OUT_X
Stereo, R
L
=8Ω, P
O
=18W
V
I
>V
IH
, V
DD
=3.6V (AVDD and
DVDD)
-
-
-
-
-
150
160
25
88
3
-
170
ο
ο
APA3160
Typ.
Max.
Unit
µA
-
-
-
C
%
kΩ
AC CHARACTERISTICS
THD+N=1%
f
in
=1kHz,
R
L
=8Ω
P
O
Output Power
THD+N=10%
f
in
=1kHz,
R
L
=8Ω
PV
DD
=18V
PV
DD
=12V
PV
DD
=8V
PV
DD
=18V
PV
DD
=12V
PV
DD
=8V
PV
DD
=18V,
P
O
=11W
THD+N
Total Harmonic Distortion Plus
Noise
f
in
=1kHz,
R
L
=8Ω
PV
DD
=12V,
P
O
=5W
PV
DD
=8V,
P
O
=2.2W
Crosstalk
PSRR
Att
Mute
Att
shutdown
S/N
V
n
Channel Separation
Power Supply Rejection Ratio
Mute Attenuation
Shutdown Attenuation
Signal to Noise Ratio
Noise Output Voltage
P
O
=1W, R
L
=8Ω, f
in
=1kHz
R
L
=8Ω
f
in
=100Hz
f
in
=1kHz
14.5
6.5
2.9
-
-
-
-
-
-
-
-
-
-
-
-
-
16
7.2
3.2
20
9
4
0.3
0.3
0.5
-95
-60
-60
-70
-110
100
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
µV
rms
dB
%
W
f
in
=1kHz, R
L
=8Ω, V
O
=1V
rms
f
in
=1kHz, R
L
=8Ω, V
O
=1V
rms
R
L
=8Ω, P
O
=16W, With
A-Weighting Filter (A
V
=0dB)
With A-Weighting Filter (A
V
=0dB)
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
f
SCLK
t
Setup1
t
Hold1
Parameter
Frequency, SCLK 32xf
S
, 48xf
S
,
64xf
S
Setup Time, LRCLK to SCLK
Rising Edge
Hold Time, LRCLK to SCLK
Rising Edge
4
Test Conditions
C
L
=30pF
APA3160
Min.
1.024
10
10
Typ.
-
-
-
Max.
12.288
-
Unit
MHz
ns
-
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
www.anpec.com.tw
APA3160
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
t
Setup2
t
Hold
Parameter
Setup Time, SDIN to SCLK
Rising Edge
Hold Time, SDIN to SCLK Rising
Edge
LRCLK Frequency
LRCLK Duty Cycle
SCLK Duty Cycle
SCLK Rising Edges Between
LRCLK Riding Edges
t
(edge)
tr/tf
(SCLK/LRCLK)
Test Conditions
APA3160
Min.
10
10
8K
40
40
32
-1/4
-
Typ.
-
-
48K
50
50
-
-
-
Max.
-
Unit
ns
-
48K
60
60
64
1/4
8
kHz
%
SCLK
edges
SCLK
period
ns
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
Rise/Fall Time for SCLK/LRCLK
Reset Timing
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Rec-
ommended Use Model” section on usage of all terminals.
Symbol
t
p(RST)
t
d(12C_Ready)
Parameter
Pulse Duration, RST Active.
Time to Enable I
2
C
Test Conditions
Min.
No Load
100
-
APA3160
Typ.
-
-
Max.
-
13.5
µs
ms
Unit
I
2
C Serial Control Port Operation
Timing characteristics for I
2
C Interface signals over recommended operating conditions (unless otherwise noted)
Symbol
f
SCL
t
W(H)
t
W(L)
t
r
t
f
t
setup1
t
hold1
t
(buf)
t
setup2
t
hold2
t
setup3
C
L
Parameter
Frequency, SCL
Pulse Duration, SCL High
Pulse Duration, SCL Low
Rise Time, SCL and SDA
Fall Time, SCL and SDA
Setup Time, SCL to SDA
Hold Time, SCL to SDA
Bus Free Time Between Stop
and Start Condition
Setup Time, SCL to Start
Condition
Hold Time, Start condition to SCL
Setup Time, SCL to Stop
Condition
Load Capacitance for Each Bus
Line
Test Conditions
No Wait States
APA3160
Min.
-
0.6
1.3
-
-
100
0
1.3
0.6
0.6
0.6
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
-
300
300
-
-
-
-
-
-
400
pF
ns
Unit
kHz
µs
µs
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
5
www.anpec.com.tw
京公网安备 11010802033920号
EEWORLD
