APA3169
20W Stereo Digital Class-D Audio Power Amplifier with EQ, DRC and 2.1
Mode
Features
General Description
The APA3169 is a digital input, stereo, high efficiency,
Class-D audio amplifier available in a TQFP7x7-48P
package.
The APA3169 accepts the digital serial audio data and
using the digital audio processor to convert the audio
data becomes the stereo Class-D output speaker
amplifier. This provides the seamless integration between
the codec and the speaker amplifier.
The APA3169 is a slave device receiving clocks from ex-
ternal source, and the Class-D’ PWM switching fre-
s
quency is 352.8kHz for the sampling rate 44.1kHz or 384
kHz for sampling 48kHz, depend on the input signal’
s
sampling rate.
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Operating Voltage: 8.0V-24V for PVDD
– 3.0V~3.6V for DVDD and AVDD
High Efficiency Class D Operation Eliminate the
Need of Heatsinks
Digital Serial Audio Input (Stereo Output)
2.1 Mode (2SE + 1BTL)
2.0 Mode (2BTL)
Single-Filter PBTL Mode Support
I
2
C Address Selection Pin (Chip Select)
I
2
C Control Interface
Sampling Rate Support from 32kHz to 192kHz
Separated Volume Control from 24dB to Mute
Soft Mute (50% Duty Cycle)
Separate Dynamic Range Control for Satellite and
Subchannels
18 Programmable Biquads for Speaker EQ and
Other Audio Processing Features
Programmable Coefficients for DRC Filters
DC Blocking Filters, De-emphasis Filters
Support for 3D Effects
Shutdown and Mute Function
Thermal and Over-Current Protections with Auto-
Recovery
Space Saving Package TQFP7x7-48P
Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
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Digital
Audio
Source
MCLK
LRCLK
SCLK
SDIN
OUT_A
LC
SE
PVDD
I
2
C
Control
SDA
SCL
A_SEL
OUT_B
LC
SE
PVDD
APA3169
Control
Input
Applications
/RESET_N
/PDN_N
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Loop Filter
LCD TV
iPod Dock
Sound Bar
PLL_FLTP
PLL_FLTM
OUT_C
LC
BTL
OUT_D
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
1
www.anpec.com.tw
APA3169
Pin Configuration
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BS_B
BS_C
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
OUT_A 1
PVDD_A 2
PVDD_A 3
BS_A 4
VCLAB 5
TM1 6
TM2 7
PBTL 8
AVSS 9
PLL_FLTM 10
PLL_FLTP 11
VR_ANA 12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OUT_D
PVDD_D
PVDD_D
BS_D
VCLCD
VREG
AGND
DGND
DVSS
DVDD
TP3
RESET_N
APA3169
Ordering and Marking Information
APA3169
Assembly Material
Handling Code
Temperature Range
Package Code
Package Code
QCA : TQFP7x7-48P
Operating Ambient Temperature Range
I : -40 to 85
o
C
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
XXXXX - Date Code
APA3169 QCA :
APA3169
XXXXX
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
2
www.anpec.com.tw
AVDD
A_SEL
MCLK
TP1
TP2
VR_DIG
PDN_N
LRCLK
SCLK
SDIN
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
TQFP7x7-48P
(TOP VIEW)
APA3169
Absolute Maximum Ratings
Symbol
V
PVDD
V
DVDD
V
AVDD
Input
Voltage
V
OUT_X
V
BS_X
T
J
T
STG
T
SDR
P
D
Supply Voltage (PVDD_X to PGND_XX)
Supply Voltage (DVDD to DVSS)
Supply Voltage (AVDD to AVSS)
Input Voltage (MCLK to AVSS)
Input Voltage (PDN, RESET, LRCLK, SCLK, SDIN, SDA, SCL to DVSS)
Input Voltage (AVSS, DVSS, AGDN to PGND_XX)
OUT_X to PGND_XX
BS_X to PGND_XX
Maximum Junction Temperature
Storage Temperature Range
Soldering Temperature Range, 10 seconds
Power Dissipation
(Note 1)
Rating
-0.3 to 26
-0.3 to 6
-0.3 to 6
-0.5 to 6
-0.5 to 6
-0.3 to +0.3
-0.3 to +26
-0.3 to +31
150
-65 to +150
260
Internally Limited
ο
ο
ο
Parameter
Unit
V
C
C
C
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
θ
JA
Parameter
Junction-to-Ambient Resistance in Free Air
(Note 2)
TQFP7x7-48P
Typical Value
25
Unit
°C/W
Note 2:
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFP7X7-48P is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
V
AVDD
, V
DVDD
V
PVDD
V
IH
V
IL
T
A
T
J
R
L
(BTL)
L
O
(BTL)
Parameter
Analog/Digital Supply Voltage (AVDD,DVDD)
Full Bridge Stage Supply Voltage (PVDD_X)
High Level Threshold
Voltage
Low Level Threshold
Voltage
Ambient Temperature Range
Junction Temperature Range
Speaker Resistance
Output Low Pass Filter Inductance
PDN, MCLK, LRCLK, SCLK,
SDIN, SDA, SCL, RESET
PDN, MCLK, LRCLK, SCLK,
SDIN, SDA, SCL, RESET
Range
Min.
3
8
2
0
-40
-40
6
10
Max.
3.6
24
5
0.8
85
125
-
47
ο
Unit
V
C
Ω
µH
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
3
www.anpec.com.tw
APA3169
Electrical Characteristics
T
A
=25 C, V
PVDD
=18V, V
AVDD
= V
DVDD
= 3.3V, R
L
=8Ω, BD Mode, f
S
=48kHz (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
PWM Operating Conditions
32 kHz Data Rate ±2%
f
S
Output Sample Rate
44.1k/88.2k/176.4 kHz Data
Rate ±2%
48k/96k/192 kHz Data Rate
± 2%
PLL Input Parameters and External Filter Components
f
MCLK
MCLK Frequency
MCLK Duty Cycle
tr/tf
(MCLK)
Rise/Fall Time for MCLK
LRCLK Allowable Drift before
LRCLK Reset
External PLL Filter Capacitor C1
External PLL Filter Capacitor C2
External PLL Filter Resistor R
DC CHARACTERISTICS
V
OH
V
OL
I
IL
I
IH
I
DD
High Level output voltage(A_SEL
and SDA)
Low Level output voltage(A_SEL
and SDA)
Low Level Input Current
High Level Input Current
3.3V Supply Current
(AVDD+DVDD)
Full Bridge Stage Supply Current
(PVDD_X)
Drain to source resistance,LS
r
DS(ON)
Drain to source resistance,HS
V
UVP
V
UVP,hyst
T
TP
Undervoltage protection limit
Undervoltage protection limit
Thermal Protection Threshold
Thermal Protection Threshold
Hysteresis
I
OH
=-4mA, DVDD=AVDD=3V
I
OL
=4mA, DVDD=AVDD=3V
V
I
<V
IL
, DVDD=AVDD=3.6V
V
I
>V
IH
, DVDD=AVDD=3.6V
Normal Mode (No LC, No load)
Reset (No LC, No load)
Normal Mode (No LC, No load)
Reset (No LC, No load)
T
J
=25
o
C, includes metallization
resistance
T
J
=25
o
C, includes metallization
resistance
PVDD falling
PVDD rising
2.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
14
18
0.5
180
180
6.8
7.2
150
30
-
0.5
75
75
20
20
36
1.6
-
-
-
-
-
o
ο
APA3169
Typ.
Max.
Unit
256
352.8
384
kHz
2.8224
40
-
-
SMD 0603 Y5V
SMD 0603 Y5V
-
-
-
-
50
-
-
47
4.7
470
24.576
60
5
4
-
-
-
MHz
%
ns
MCLKs
nF
Ω
V
V
µA
µA
mA
I
PVDD
mΩ
mΩ
V
V
C
-
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
4
www.anpec.com.tw
APA3169
Electrical Characteristics (Cont.)
T
A
=25 C, V
PVDD
=18V, V
AVDD
= V
DVDD
= 3.3V, R
L
=8Ω, BD Mode, f
S
=48kHz (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
DC CHARACTERISTICS (CONT.)
OLPC
I
OC
I
OCT
R
OUT
Overload protection counter
Overcurrent limit protection
Overcurrent response time
Internal pull-down resistance at
each OUT_X
Ccaopnanceitcoter dchwahrgeen.
drivers are tristated to provide
bootstrap
f
PWM
=384kHz
Resistor - programmable, max.
current
-
-
-
-
0.63
4.5
150
3
-
-
-
-
ms
A
ns
kΩ
APA3169
Typ.
Max.
Unit
ο
AC CHARACTERISTICS
V
PVDD
=18V
BTL,THD+N=1%,
f
in
=1kHz,R
L
=8Ω
V
PVDD
=12V
V
PVDD
=8V
BTL,THD+N=10
%,f
in
=1kHz,R
L
=8
Ω
P
O
Output Power
PBTL,THD+N=1
%,f
in
=1kHz,R
L
=4
Ω
PBTL,THD+N=1
0%,f
in
=1kHz,R
L
=
4Ω
SE,THD+N=1%,f
i
n
=1kHz,R
L
=4Ω
SE,THD+N=10%
,f
in
=1kHz,R
L
=4Ω
V
PVDD
=18V
V
PVDD
=12V
V
PVDD
=8V
V
PVDD
=18V
V
PVDD
=12V
V
PVDD
=18V
V
PVDD
=12V
V
PVDD
=18V
V
PVDD
=12V
V
PVDD
=18V
V
PVDD
=12V
14.5
6.5
2.9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
7.2
3.2
20
9
4
30.5
13.7
37.1
16.9
7.5
3.4
9.5
4.3
0.06
0.13
0.2
200
-72
95
-70
-110
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
µVms
%
W
THD+N
Total Harmonic Distortion Plus
Noise
Vn
Crosstalk
SNR
Att
Mute
Att
shutdown
Noise Output Voltage
Channel Separation
Signal to Noise Ratio
Mute Attenuation
Shutdown Attenuation
V
PVDD
=18V,
Po=1W
V
PVDD
=12V,
f
in
=1kHz,R
L
=8Ω
Po=1W
V
PVDD
=8V,
Po=1W
With A-Weighting Filter
(Volume=0dB)
P
O
=0.25W, R
L
=8Ω, f
in
=1kHz
R
L
=8Ω, Po=16W, A-Weighting
Filter (Volume =0dB)
f
in
=1kHz, R
L
=8Ω, V
O
=1V
rms
f
in
=1kHz, R
L
=8Ω, V
O
=1V
rms
Copyright
©
ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
5
www.anpec.com.tw
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