U62H824PA
Automotive Fast 8K x 24 SRAM
Features
Description
The U62H824PA is a static RAM
manufactured using a CMOS pro-
cess technology. The device inte-
grates an 8K x 24 SRAM core with
multiple chip enable inputs, output
enable, and an externally control-
led single address pin multiplexer.
These functions allow for direct
connection
to
the
Motorola
DSP56k Digital Signal Processor
Family and provide a very efficient
means for implementation of a
reduced parts count system requi-
ring no additional interface logic.
The avialability of multiple chip
enable (E1 and E2) and output
enable (G) inputs provides for
greater system flexibility when mul-
tiple devices are used. With either
chip enable unasserted, the device
will enter standby mode, useful in
low-power applications. A single
on-chip multiplexer selects A12 or
X/Y as the highest order address
input depending upon the state of
the V/S control input. This feature
allows one physical static RAM
component to efficiently store pro-
gram and vector or scalar ope-
rands
by
dynamically
re-
partitioning the RAM array.
Typical applications will logically
map vector operands into upper
memory with scalar operands
being stored in lower memory.
An application example is at the
end of this document for additional
information.
Multiple power and ground pins
have been utilized to minimize
effectes induced by output noice.
F
196 608 bit static CMOS RAM
F
35 ns Access Time
F
Fully static Read and Write
operations
F
Equal address and chip
enable access times
F
Single bit on-chip address
multiplexer
F
Active high and active low
chip enable inputs
F
Output enable controlled three-
state outputs
F
TTL/CMOS-compatible
F
Low power standby mode
F
Power supply voltage 5 V
F
Operating temperature range
-40
°C
to 125
°C
F
CECC 90000 Quality Standard
F
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F
Latch-up immunity > 100 mA
F
Package: PLCC52
Pin Configuration
VCC
A10
A11
A12
X/Y
V/S
NC
A0
A1
A2
A3
A4
A5
Pin Description
7
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
8
9
10
11
12
13
14
15
16
17
18
19
20
6
5
4
3
2
1 52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
34
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
Signal Name
A0 - A11
A12, X/Y
V/S
DQ0 - DQ23
E1, E2
G
W
VCC
VSS
NC
Signal Description
Address Inputs
Multiplexed Address
Address Multiplexer Control
Data Input / Output
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Not Connected
For proper operation of the device, all V
SS
pins
must be connected to ground.
21 22 23 24 25 26 27 28 29 30 31 32 33
E1
E2
DQ12
DQ11
A9
A8
A7
A6
VCC
VSS
W
NC
G
December 12, 1997
1
U62H824PA
Block Diagram
A0
Memory Cell
Row
A5
A10
A11
Decoder
Array
256 Rows x
768 Columns
V
CC
V
SS
DQ0
DQ23
Input Data
Control
Column I/O
E1
E2
W
G
Column Decoder
&
&
X/Y
A12
V/S
1 Q A12i
0
2 to 1 MUX
A6
(LSB)
(MSB)
A9
&
Truth Table
E1
H
X
L
L
L
L
L
E2
X
L
H
H
H
H
H
G
X
X
H
L
L
X
X
W
X
X
H
H
H
L
L
V/S
X
X
X
H
L
H
L
Mode
Not Selected
Not Selected
Output Disable
Read Using X/Y
Read Using A12
Write Using X/Y
Write Using A12
Supply
Current
I
CC(SB)
I
CC(SB)
I
CC(OP)
I
CC(OP)
I
CC(OP)
I
CC(OP)
I
CC(OP)
I/O
Status
High - Z
High - Z
High - Z
Data Out
Data Out
Data In
Data In
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times and t
en
-times, in which cases transition is measured
±
200 mV from steady-state voltage.
Recommended
Operating Conditions
Power Supply Voltage
Input Low Voltage *
Input High Voltage
*
-2 V at Pulse Width
≤
10 ns
Symbol
V
CC
V
IL
V
IH
Conditions
Min.
4.5
-0.3
2.2
Max.
5.5
0.8
V
CC
+ 0.3
Unit
V
V
V
2
December 12, 1997
U62H824PA
Maximum Ratings
Power Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Output Short-Circuit Current
at V
CC
= 5 V and V
O
= 0 V
**
Symbol
V
CC
V
I
V
O
P
D
T
a
T
stg
|I
OS
|
Min.
-0.5
-0.5
-0.5
-
-40
-65
Max.
7
V
CC
+ 0.5
V
CC
+ 0.5
1.75
125
150
20
Unit
V
V
V
W
°C
°C
mA
** Not more than 1 output should be shorted at the same time. Duration of the short circuit should not execeed 30 s.
Electrical Characteristics
Supply Current - Operating Mode
Symbol
I
CC(OP)
Conditions
V
CC
V
E1
V
E2
V
G
other inputs
I
out
t
cW
V
CC
V
E1
V
E2
all inputs
=
=
=
=
=
=
=
5.5 V
0.8 V
2.2 V
2.2 V
V
IL
or V
IH
0 mA
35 ns
Min.
Max.
Unit
180
10
mA
mA
Supply Current - Standby Mode
(CMOS level)
I
CC(SB)
= 5.5 V
= V
CC
- 0.2 V
= 0.2 V
≥
V
CC
- 0.2 V
or
≤
0.2 V
=
=
=
=
5.5 V
2.2 V
0.8 V
V
IH
or V
IL
2.4
Supply Current - Standby Mode
(TTL level)
I
CC(SB)1
V
CC
V
E1
V
E2
all inputs
V
CC
I
OH
I
OL
V
CC
V
IH
V
IL
V
CC
V
OH
V
OL
V
CC
V
OH
V
OL
V
G
15
mA
Output High Voltage
Output Low Voltage
Input High Leakage Current
Input Low Leakage Current
Output High Current
Output Low Current
Output Leakage Current
High at Three-State Outputs
Low at Three-State Outputs
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
I
OHZ
I
OLZ
= 4.5 V
= -4.0 mA
= 8.0 mA
= 5.5 V
= 5.5 V
= 0 V
= 4.5 V
= 2.4 V
= 0.4 V
= 5.5 V
= 5.5 V
= 0 V
= V
IH
V
0.4
2
V
µA
µA
-4
mA
mA
2
µA
µA
-2
8
-2
December 12, 1997
3
U62H824PA
Switching Characteristics
Read Cycle
Read Cycle Time
Address Access Time to Data Valid
MUX Control to Data Valid
Chip Enable Access Time to Data Valid
G LOW to Data Valid
Output Hold Time from Address Change
Output Hold Time from MUX Control Change
E1 LOW or E2 HIGH to Output in Low-Z
G LOW to Output in Low-Z
E1 HIGH or E2 LOW to Output in High-Z
G HIGH to Output in High-Z
t
LZCE
t
LZOE
t
HZCE
t
HZOE
t
ACE
t
OE
t
OH
Symbol
Alt.
t
RC
t
AA
IEC
t
cR
t
a(A)
t
a(VS)
t
a(E)
t
a(G)
t
v(A)
t
v(VS)
t
en(E)
t
en(G)
t
dis(E)
t
dis(G)
5
5
0
0
15
15
Min.
35
35
35
35
15
ns
ns
ns
ns
ns
ns
ns
ns
35
Max.
Unit
ns
ns
Switching Characteristics
Write Cycle
Write Cycle Time
Write Pulse Width
Write Pulse Width Setup Time
Address Setup Time
MUX Control Setup Time
Address Valid to End of Write
MUX Control Valid to End of Write
Adress Valid to End of Write
MUX Control Valid to End of Write
Chip Enable Setup Time
Pulse Width Chip Enable
Data Setup Time
Data Hold Time
Address Hold from End of Write
MUX Control from End of Write
W HIGH to Output in Low-Z
W LOW to Output in High-Z
Symbol
Alt.
t
WC
t
WP
t
WP
t
AS
IEC
t
cW
t
w(W)
t
su(W)
t
su(A)
t
su(VS)
t
AW
t
su(A-WH)
t
su(VS-WH)
t
su(A-E)
t
su(VS-E)
t
CW
t
CW
t
DS
t
DH
t
AH
t
su(E)
t
w(E)
t
su(D)
t
h(D)
t
h(A)
t
h(VS)
t
LZWE
t
HZWE
t
en(W)
t
dis(W)
Min.
35
20
20
0
0
30
30
30
30
20
20
15
0
0
0
5
35
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
4
December 12, 1997
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