AS7C331MPFS36A-200BC datasheet, PDF

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AS7C331MPFS36A-200BC: DescriptionStandard SRAM, 1MX36, 3.1ns, CMOS, PBGA165, BGA-165; Categorystorage storage; File Size639KB，27 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C331MPFS36A-200BC Overview

Standard SRAM, 1MX36, 3.1ns, CMOS, PBGA165, BGA-165

AS7C331MPFS36A-200BC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.1 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	37748736 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.46 mm
Maximum standby current	0.06 A
Minimum standby current	3.14 V
Maximum slew rate	0.4 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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November 2004

AS7C331MPFS32A

AS7C331MPFS36A

3.3V 1M

32/36 pipelined burst synchronous SRAM

Features

•

Organization: 1,048,576 words × 32 or 36 bits

Fast clock speeds to 200 MHz

Fast clock to data access: 3.1/3.5/3.8 ns

Fast OE access time: 3.1/3.5/3.8 ns

Fully synchronous register-to-register operation

Single-cycle deselect

Asynchronous output enable control

Available in 100-pin TQFP and 165-ball BGA packages

Individual byte write and global write

Multiple chip enables for easy expansion

•

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Linear or interleaved burst control

Snooze mode for reduced power-standby

Common data inputs and data outputs

Boundary Scan using IEEE 1149.1 JTAG function is avail-

able in 165 Ball BGA Package only.

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[19:0]

CLK

CLR

Burst logic

Address

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

1M × 32/36

Memory

array

32/36

GWE

BWE

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

32/36

DQ[a:d]

Selection guide

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-200

200

3.1

450

170

-166

166

3.5

400

150

-133

7.5

133

3.8

350

140

Units

MHz

11/29/04, v.2.8

Alliance Semiconductor

1 of 27

AS7C331MPFS32A

AS7C331MPFS36A

Functional description

The AS7C331MPFS32A/36A is a high-performance CMOS 32-Mbit Synchronous Static Random Access Memory (SRAM)

device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any

given technology.

Fast cycle times of 5/6/7.5 ns with clock access times (t

) of 3.1/3.5/3.8 ns enable 200,166and 133MHz bus frequencies.

Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller

address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally

generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In

a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next

access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the

LBO

input.

With

LBO

unconnected or driven high, burst operations use an interleaved count sequence. With

LBO

driven low, the device

uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more

bytes may be written by asserting BWE and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.

Address is incremented internally to the next burst address if BWn and ADV are sampled low. This device operates in single-

cycle deselect feature during read cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP follow.

ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C331MPFS32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can

operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP and 165-ball BGA.

TQFP and BGA capacitance

Parameter

Input capacitance

I/O capacitance

* Guaranteed not tested

Symbol

IN*

I/O*

Test conditions

= 0V

OUT

= 0V

Min

Max

Unit

TQFP and BGA thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

1–layer

4–layer

Symbol

Typical

Units

°C/W

11/29/04, v.2.8

Alliance Semiconductor

5 of 27

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