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V54C3256804VDS7IPC

Description
Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA60, MO-210, FBGA-60
Categorystorage    storage   
File Size720KB,56 Pages
ManufacturerProMOS Technologies Inc
Download Datasheet Parametric View All

V54C3256804VDS7IPC Overview

Synchronous DRAM, 32MX8, 5.4ns, CMOS, PBGA60, MO-210, FBGA-60

V54C3256804VDS7IPC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerProMOS Technologies Inc
Parts packaging codeBGA
package instructionTFBGA, BGA60,8X15,32
Contacts60
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)143 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PBGA-B60
JESD-609 codee0
length13 mm
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals60
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA60,8X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.001 A
Maximum slew rate0.2 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm
V54C3256(16/80/40)4VD*I
256Mbit SDRAM, INDUSTRIAL TEMPERATURE
3.3 VOLT, TSOP II / FBGA PACKAGE
16M X 16, 32M X 8, 64M X 4
6
System Frequency (f
CK
)
Clock Cycle Time (t
CK3
)
Clock Access Time (t
AC3
) CAS Latency = 3
Clock Access Time (t
AC2
) CAS Latency = 2
166 MHz
6 ns
5.4 ns
5.4 ns
7PC
143 MHz
7 ns
5.4 ns
5.4 ns
7
143 MHz
7 ns
5.4 ns
6 ns
Features
4 banks x 4Mbit x 16 organization
4 banks x 8Mbit x 8 organization
4 banks x16Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8, and full page for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II, 60 Ball FBGA, 54
Ball FBGA
LVTTL Interface
Single (3.0V~3.3 V)±0.3 V Power Supply
Industrial Temperature (TA): -40C to +85C
Description
The V54C3256(16/80/40)4VD*I is a four bank
Synchronous DRAM organized as 4 banks x 4Mbit
x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4.
The V54C3256(16/80/40)4VD*I achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
-40°C to +85°C
Package Outline
T/S
Access Time (ns)
6
Power
7
7PC
Std.
L
U
Temperature
Mark
I
V54C3256(16/80/40)4VD*I Rev. 1.3 December 2007
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