PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD65949S1-P00-F6
BONITO
TM
- Companion Chip
for V
R
43xx and V
R
5xxx
DESCRIPTION
‘Bonito’ is a system controller especially designed for MIPS
®
RISC microprocessors with a 32-bit SysAD bus.
‘Bonito’ incorporates a simple and fast memory interface for PC-100 compliant SDRAMs, a Rev 2.1 compliant
33 MHz/32-bit PCI interface and last but not least a 16-bit local bus with IDE support. It has a built-in, flexible
interrupt controller and numerous general purpose I/Os. In applications using the 32-bit SysAD bus (e.g. V
R
43xx,
V
R
5432 and V
R
5500 based systems) it reduces the number of required parts significantly. ‘Bonito’ comes in a
compact 352-pin plastic BGA package.
‘Bonito’ is designed as system controller for MIPS
®
RISC CPU based systems. The combination of ‘Bonito’ with a
MIPS
®
RISC microprocessor gives you an excellent performance/cost ratio for computing or data traffic intensive
applications like high resolution printers, scanners, networking equipment, high end Set-Top-Boxes or
PC-Peripherals.
Functions in detail are described in Bonito's specification.
The latest version of this specification can be downloaded from Algorithmics' website:
www.algor.co.uk
Be sure to read this specification when you design your systems.
FEATURES
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Direct connection to any MIPS R4x00 CPU with
a 32-bit SysAD bus
Direct connection to 32-bit 33 MHz PCI bus,
conforming to Rev. 2.1
Integrated PCI arbiter acting as PCI master or target
Independent CPU and PCI input clocks
Internal ‘cache’ for local memory locations provides
greatly enhanced PCI transfer performance for
device controllers which are PCI bus initiators
PCI/local-memory copier for applications requiring
bulk data transport
16-bit local I/O bus for local ROM and ‘slow’
peripherals
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High performance SDRAM memory interface using
standard PC-100 parts in either 32- or 64-bit arrays,
including 100-, 144- or 168- pin DIMMs
DMA support for faster devices on the local I/O bus,
including ‘UDMA’ transfers as defined in the ATA-4
standard for PC disk drives
Configurable debug mode
Glueless support of CPU reset sequence
Includes useful generic interrupt controller
Configurable from ROM, pins or PCI bus
Supports all V
R
43xx, V
R
5432 and V
R
5500 bus
modes
Operating voltage: 3.3 V, 5 V tolerant I/O
Compact 352-pin 1.27 mm pitch BGA package
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ORDERING INFORMATION
Device
Bonito
Part Number
µPD65949S1-P00-F6
Package
352 P-BGA
Operating Frequency
91 MHz
The information contained in this document is released in advance of the production cycle for the device.
The parameters for the device may change before final production, or NEC Corporation may, at its own
discretion, withdraw the device prior to production.
NEC Corporation 2002
Document No. U15789EE1V0DS00
Data Published: February 2002
Embedded System
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