ML145502
ML145503
ML145505
PCM Codec–Filter Mono–Circuit
Legacy Device:
Motorola MC145502, MC145503, MC145505
The ML145502, ML145503, and ML145505 are all per channel PCM
Codec–Filter mono–circuits. These devices perform the voice digitization
and reconstruction as well as the band limiting and smoothing required
for PCM systems. The ML145503 is a general purpose device that is
offered in a 16–pin package. These are designed to operate in both syn-
chronous and asynchronous applications and contain an on–chip preci-
sion reference voltage. The ML145505 is a synchronous device offered in
a 16–pin DIP and wide body SOIC package intended for instrument use.
The ML145502 is the full–featured device which presents all of the
options of the chip. This device is packaged in a 22–pin DIP and a
28–pin chip carrier package
These devices are pin–for–pin replacements for Motorola’s first genera-
tion of MC14400/01/02/03/05 PCM mono–circuits and are upwardly
compatible with the MC14404/06/07 codecs and other industry standard
codecs. They also maintain compatibility with Motorola’s family of
MC33120 and MC3419 SLIC products.
The ML1455xx family of PCM Codec–Filter mono–circuits utilizes
CMOS due to its reliable low–power performance and proven capability
for complex analog/digital VLSI functions.
ML145502
• 22 Pin and 28 Pin Packages
• Transmit Bandpass and Receive Low–Pass Filter On–Chip
• Pin Selectable Mu–Law/A–Law Companding with Corresponding
Data Format
• On–Chip Precision Reference Voltage (3.15 V)
• Power Dissipation of 50 mW, Power–Down of 0.1 mW at ±5 V
• Automatic Prescaler Accepts 128 kHz, 1.536, 1.544, 2.048, and 2.56
MHz for Internal Sequencing
• Selectable Peak Overload Voltages (2.5, 3.15, 3.78 V)
• Access to the Inverting Input of the TxI Input Operational Amplifier
• Variable Data Clock Rates (64 kHz to 4.1 MHz)
• Complete Access to the Three Terminal Transmit Input Operational
Amplifiers
• An External Precision Reference May Be Used
ML145503—
Similar to the ML145502 Plus:
• 16–Pin Dip and SOIC 16 Packages
• Complete Access to the Three Terminal Transmit Input Operational
Amplifiers
ML145505
— Somewhat Similar To ML145503 Except:
• Common 64 kHz to 4.1 MHz Transmit/Receive Data Clock
16
1
P DIP 16 = EP
PLASTIC DIP
CASE 648
22
1
P DIP 22 = WP
PLASTIC DIP
CASE 708
16
1
SOG 16 = -5P
SOG PACKAGE
CASE 751G
28 1
PLCC 28 = -4P
PLCC PACKAGE
CASE 776
CROSS REFERENCE/ORDERING INFORMATION
LANSDALE
PACKAGE
MOTOROLA
P DIP 22
PLCC 28
P DIP 16
SO 16W
P DIP 16
SO 16W
MC145502P
MC145502FN
MC145503P
MC145503DW
MC145505P
MC145505DW
ML145502WP
ML145502-4P
ML145503EP
ML145503-5P
ML145505EP
ML145505-5P
Note:
Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from
ML
to
MLE.
Page 1 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ML145502/03/05 PCM CODEC–FILTER MONO–CIRCUIT BLOCK DIAGRAM
RDD
RCE
RDC
RxO
Rx
RxG
Rx
RxO
VDD
VSS
VAG
1
FREQUENCY
D/A
RECEIVE SHIFT
REGISTER
–
+
VDD
400
µA
SHARED
DAC
CCI PRESCALER
+
–
2.5 V
REF
SEQUENCE
AND
CONTROL
RSI
CIRCUITRY
TRANSMIT SHIFT
REGISTER
÷
1, 12, 16, 20
CCI
MSI
VLS
PDI
Vref
RSI
TxI
– Tx
+ Tx
NOTES:
–
VSS
TDD
TDE
TDC
A/D
+
FREQUENCY
FREQUENCY
Controlled by VLS
Rx
≈
100 kΩ (internal resistors)
Page 2 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
PIN ASSIGNMENTS
(DRAWINGS DO NOT REFLECT RELATIVE SIZE)
ML145503EP
VAG
RxO
+ Tx
TxI
– Tx
Mu/A
PDI
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
RDD
RCE
RDC
TDC
TDD
TDE
VLS
VAG
RxO
+ Tx
TxI
– Tx
Mu/A
PDI
VSS
ML145505EP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
RDD
RCE
DCLK
CCI
TDD
TDE
VLS
ML145502WP
Vref
VAG
RxO
RxG
RxO
+ Tx
TxI
– Tx
Mu/A
PDI
VSS
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
RSI
VDD
RDD
RCE
RDC
TDC
CCI
TDD
TDE
MSI
VLS
VAG
RxO
+ Tx
TxI
– Tx
Mu/A
PDI
VSS
ML145503-5P
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
RDD
RCE
RDC
TDC
TDD
TDE
VLS
VAG
RxO
+ Tx
TxI
– Tx
Mu/A
PDI
VSS
ML145505-5P
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
RDD
RCE
DCLK
CCI
TDD
TDE
VLS
RxG
RxO
+ Tx
NC
NC
TxI
– Tx
ML145502-4P
RxO
VAG
Vref
NC
RSI
VDD
RDD
4 3 2 1 28 27 26
5
25
24
6
7
23
22
8
28–PIN PQLCC
(TOP VIEW)
9
21
20
10
11
19
12 13 14 15 16 17 18
Mu/A
PDI
VSS
NC
V LS
MSI
TDE
NC = NO CONNECTION
RCE
RDC
TDC
NC
NC
CCI
TDD
Page 3 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS
(Voltage Referenced to VSS)
Rating
DC Supply Voltage
Voltage, Any Pin to VSS
DC Drain Per Pin (Excluding VDD, VSS)
Operating Temperature Range
Storage Temperature Range
Symbol
VDD, VSS
V
I
TA
Tstg
Value
– 0.5 to 13
– 0.5 to VDD + 0.5
10
– 40 to + 85
– 85 to + 150
Unit
V
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
(TA = – 40 to + 85°C)
Characteristic
DC Supply Voltage
Dual Supplies: VDD = – VSS, (VAG = VLS = 0 V)
Single Supply: VDD to VSS (VAG is an Output, VLS = VDD or VSS)
ML145502, ML145503, ML145505 (Using Internal 3.15 V Reference)
ML145502 Using Internal 2.5 V Reference
ML145502 Using Internal 3.78 V Reference
ML145502 Using External 1.5 V Reference, Referenced to V AG
Power Dissipation
CMOS Logic Mode (VDD to VSS = 10 V, VLS = VDD)
TTL Logic Mode (VDD = + 5 V, VSS = – 5 V, VLS = VAG = 0 V)
Power Down Dissipation
Frame Rate Transmit and Receive
Data Rate
ML145503
Must Use One of These Frequencies, Relative to MSI Frequency of 8 kHz
This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For
proper operation it is recommended that Vin
and Vout be constrained to the range VSS (Vin
or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., VSS, VDD,
VLS, or VAG).
Min
4.75
8.5
7.0
9.5
4.75
—
—
—
7.5
—
—
—
—
—
64
—
—
—
—
—
—
—
Typ
5.0
—
—
—
—
40
50
0.1
8.0
128
1536
1544
2048
2560
—
3.15
3.78
3.15
2.5
1.51 x Vref
1.26 x Vref
Vref
Max
6.3
12.6
12.6
12.6
12.6
mW
70
90
1.0
8.5
—
—
—
—
—
4096
—
—
—
—
—
—
—
mW
kHz
kHz
Unit
V
Data Rate for ML145502, ML145505
Full Scale Analog Input and Output Level
ML145503, ML145505
ML145502 (Vref = VSS )
ML145502 Using an External Reference V oltage Applied at Vref Pin
kHz
Vp
RSI = VDD
RSI = VSS
RSI = VAG
RSI = VDD
RSI = VSS
RSI = VAG
DIGITAL LEVELS
(VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85°C)
Characteristic
Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDI)
CMOS Mode (VLS = VDD, VSS is Digital Ground)
TTL Mode (VLS
≤
VDD – 4.0 V, VLS is Digital Ground)
“0”
“1”
“0”
“1”
Symbol
VIL
VIH
VIL
VIH
Min
—
0.7 x VDD
—
VLS + 2.0 V
Max
0.3 x VDD
—
VLS + 0.8 V
—
mA
IOL
IOH
IOL
IOH
1.0
3.0
– 1.0
– 3.0
1.6
– 0.2
—
—
—
—
—
—
Unit
V
Output Current for TDD (Transmit Digital Data)
CMOS Mode (VLS = VDD, VSS = 0 V and is Digital Ground)
(VDD = 5 V, Vout = 0.4 V)
(VDD = 10 V, Vout = 0.5 V)
(VDD = 5 V, Vout = 4.5 V)
(VDD = 10 V, Vout = 9.5 V)
TTL Mode (VLS
≤
VDD – 4.75 V, VLS = 0 V and is Digital Ground)
(VOL = 0.4 V)
(VOH = 2.4 V)
Page 4 of 26
www.lansdale.com
Issue A
ML145502, ML145503, ML145505
LANSDALE Semiconductor, Inc.
ANALOG TRANSMISSION PERFORMANCE
(VDD = + 5 V
±
5%, VSS = – 5 V
±
5%, VLS = VAG = 0 V, Vref = RSI = VSS (Internal 3.15 V Reference), 0 dBm0 = 1.546 Vrms = + 6 dBm @
600
Ω,
TA = – 40 to + 85°C, TDC = RDC = CC = 2.048 MHz, TDE = RCE = MSI = 8 kHz, Unless Otherwise Noted)
End–to–End
Characteristic
Absolute Gain (0 dBm0 @ 1.02 kHz, TA = 25°C, VDD = 5 V, VSS = – 5 V)
Absolute Gain Variation with Temperature 0 to + 70°C
Absolute Gain Variation with Temperature – 40 to +85°C
Absolute Gain Variation with Power Supply (VDD = 5 V, VSS = – 5 V, 5%)
Gain vs Level Tone (Relative to – 10 dBm0, 1.02 kHz)
+ 3 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
Min
—
—
—
—
– 0.4
– 0.8
– 1.6
—
—
—
35
29
24
27.5
35
33.1
28.2
13.2
—
—
—
– 0.3
– 1.6
—
—
—
300 to 3000 Hz
Out–of–Band Spurious at RxO (300 – 3400 Hz @ 0 dBm0 In)
4600 to 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
Idle Channel Noise Selective @ 8 kHz, Input = VAG, 30 Hz Bandwidth
Absolute Delay @ 1600 Hz (TDC = 2.048 MHz, TDE = 8 kHz)
Group Delay Referenced to 1600 Hz (TDC = 2048 kHz,
TDE = 8 kHz)
500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
dB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
– 30
– 40
– 30
– 70
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
310
200
140
70
40
75
110
170
– 75
– 41
—
—
—
—
—
– 40
– 40
– 30
– 20
—
—
—
—
—
– 30
– 40
– 30
– 70
180
—
—
—
—
90
120
160
– 80
– 41
dB
dB
dBm0
µs
µs
Max
—
—
—
—
+ 0.4
+ 0.8
+ 1.6
—
—
—
—
—
—
—
—
—
—
—
15
– 69
– 23
+ 0.3
0
– 28
– 60
—
Min
– 0.30
—
—
—
– 0.2
– 0.4
– 0.8
– 0.25
– 0.30
– 0.45
36
29
24
28
35.5
33.5
28.5
13.5
—
—
—
– 0.15
– 0.8
—
—
—
A/D
Max
+ 0.30
±
0.03
±
0.1
±
0.02
+ 0.2
+ 0.4
+ 0.8
+ 0.25
+ 0.30
+ 0.45
—
—
—
—
—
—
—
—
15
– 69
– 23
+ 0.15
0
– 14
– 32
– 43
Min
– 0.30
—
—
—
– 0.2
– 0.4
– 0.8
– 0.25
– 0.30
– 0.45
36
30
25
28.5
36
34.2
30.0
15.0
—
—
—
– 0.15
– 0.8
—
—
—
D/A
Max
+ 0.30
±
0.03
±
0.1
±
0.02
+ 0.2
+ 0.4
+ 0.8
+ 0.25
+ 0.30
+ 0.45
—
—
—
—
—
—
—
—
9
– 78
0.15
+ 0.15
0
– 14
– 30
– 43
dBC
Unit
dB
dB
dB
dB
dB
Gain vs Level Pseudo Noise (A–Law Relative to – 10 dBm0)
CCITT G.714
– 10 to – 40 dBm0
– 40 to – 50 dBm0
– 50 to – 55 dBm0
Total Distortion – 1.02 kHz Tone (C–Message)
0 to – 30 dBm0
– 40 dBm0
– 45 dBm0
– 3 dBm0
– 6 to – 27 dBm0
– 34 dBm0
– 40 dBm0
– 55 dBm0
dB
Total Distortion With Pseudo Noise (A–Law)
CCITT G.714
dB
Idle Channel Noise (For End–End and A/D, See Note 1)
Mu–Law, C–Message Weighted
A–Law, Psophometric Weighted
Frequency Response (Relative to 1.02 kHz @ 0 dBm0)
15 to 60 Hz
300 to 3000 Hz
3400 Hz
4000 Hz
4600 Hz
dBrnC0
dBm0p
dB
Inband Spurious (1.02 kHz @ 0 dBm0, Transmit and RxO)
dBm0
Crosstalk of 1020 Hz @ 0 dBm0 From A/D or D/A (Note 2)
Intermodulation Distortion of Two Frequencies of Amplitudes – 4 to
– 21 dBm0 from the Range 300 to 3400 Hz
NOTES:
1. Extrapolated from a 1020 Hz @ – 50 dBm0 distortion measurement to correct for encoder enhancement.
2. Selectively measured while the A/D is stimulated with 2667 Hz @ – 50 dBm0.
Page 5 of 26
www.lansdale.com
Issue A
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