Intel StrataFlash
£
Wireless Memory
System (LV18/LV30 SCSP)
1024-Mbit LV Family
Datasheet
Product Features
■
■
■
■
■
Device Architecture
— Flash die density: 128-, 256-Mbit
— Top or Bottom flash parameter
configuration
Device Voltage
— Core: V
CC
= 1.8 V (Typ)
— I/O: V
CCQ
= 1.8 V or 3.0 V (Typ)
Device Common Performance
— Buffered EFP: 5
µs
/ Byte (Typ) per die
— Buffer Program: 7
µs
/ Byte (Typ) per
die
— Concurrent Buffered EFP: 6.4 Mbits
per second (4 dies)
Device Common Architecture
— Asymmetrical blocking structure
— 16-KWord parameter blocks (Top or
Bottom); 64-KWord main blocks
— Zero-latency block locking
— Absolute write protection with block
lock down using F-WP#
Device Packaging
— 88 balls (8 x 10 active ball matrix) for
LVQ device and 103 balls (9 x 12 ball
matrix) for LVX device
— Area: 8 x 11 mm to 11 x 11 mm
— Height: 1.2 mm to 1.4 mm
■
■
■
■
■
■
Code Segment Flash Performance
— 85 ns initial access at 1.8 V I/O
— 25 ns async page read at 1.8 V I/O
— 14 ns sync read (t
CHQV
) at 1.8 V I/O
— 54 MHz CLK at 1.8 V I/O
Data Segment Flash Performance
— 170 ns initial access at 1.8 V I/O
— 55 ns async page read at 1.8 V I/O
Code Segment Flash Architecture
— Hardware Read-While-Write/Erase
— Multiple 8-Mbit or 16-Mbit Partition Sizes
— 2-Kbit One-Time Programmable (OTP)
protection register
Data Segment Flash Architecture
— Software Read-While-Write/Erase
— Single Partition Size Die
Flash Software
— Intel
£
FDI, Intel
£
PSM, and Intel
£
VFM
— Common Flash Interface (CFI)
— Basic/Extended Command Set
Quality and Reliability
— Extended Temp:
–
25
°C
to +85
°C
— Minimum 100 K flash block erase cycle
— 0.13
µm
ETOX¥ VIII flash technology
The Intel StrataFlash
®
Wireless Memory System (LV18/LV30 SCSP) family offers a variety of
high performance code segment and large embedded data segment combination flash dies in
common package footprints and ballouts on 0.13 µm ETOX™ VIII flash technology. The code
segment flash features 1.8 V low-power operations with flexible multi-partitions, dual operation
Read-While-Write/Erase, asynchronous and synchronous reads at 54 MHz. The data segment flash
features 1.8 V low-power operations optimized for cost sensitive large embedded asynchronous
data application. The LV device integrates up to two code segment flash dies and two data segment
flash dies compatible with other LQ/LVQ or LX/LVX SCSP family ballout packages.
Notice:
This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
253854-003
February 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel StrataFlash
®
Wireless Memory System (LV18/LV30 SCSP), 1024-Mbit LV Family
may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2004.
*Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0 Introduction
...............................................................................................................................7
1.1
1.2
1.3
2.1
2.2
Nomenclature .......................................................................................................................7
Acronyms ..............................................................................................................................8
Conventions..........................................................................................................................9
Product Description ............................................................................................................10
Product Segment Unique Features ....................................................................................12
2.2.1 Code Segment Die ................................................................................................12
2.2.2 Data Segment Die .................................................................................................13
2.2.3 xRAM Segment Die ...............................................................................................13
Product Configurations and Memory Partitioning ...............................................................13
Memory Map .......................................................................................................................16
Three Flash Dies: QUAD+ SCSP Mechanical Spec...........................................................19
Four Flash Dies: x16D Performance SCSP Mechanical Spec ...........................................20
Signal Ballout......................................................................................................................21
Signal Descriptions .............................................................................................................23
Absolute Maximum Ratings ................................................................................................25
Operating Conditions ..........................................................................................................26
DC Current Characteristics .................................................................................................27
DC Voltage Characteristics.................................................................................................28
AC Test Conditions.............................................................................................................29
Capacitance ........................................................................................................................30
AC Read Specifications ......................................................................................................30
AC Write Specifications ......................................................................................................37
Program and Erase Characteristics ....................................................................................41
Power-Up and Down...........................................................................................................42
Reset ..................................................................................................................................42
Power Supply Decoupling...................................................................................................43
Automatic Power Saving (APS) ..........................................................................................43
Bus Operations ...................................................................................................................44
9.1.1 Reads ....................................................................................................................45
9.1.2 Writes.....................................................................................................................45
2.0 Functional Overview
............................................................................................................10
2.3
2.4
3.1
3.2
4.1
4.2
5.1
5.2
6.1
6.2
7.1
7.2
7.3
7.4
7.5
8.1
8.2
8.3
8.4
9.1
3.0 Package Information
............................................................................................................18
4.0 Ballout and Signal Descriptions
......................................................................................21
5.0 Maximum Ratings and Operating Conditions
...........................................................25
6.0 Electrical Specifications
.....................................................................................................27
7.0 AC Characteristics
................................................................................................................29
8.0 Power and Reset Specifications
.....................................................................................42
9.0 Design Guide: Operation Overview
...............................................................................44
Datasheet
3
Contents
9.2
9.3
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
11.1
11.2
11.3
11.4
11.5
11.6
9.1.3 Output Disable ....................................................................................................... 46
9.1.4 Standby.................................................................................................................. 46
9.1.5 Reset ..................................................................................................................... 46
Flash Device Commands.................................................................................................... 47
Command Definitions ......................................................................................................... 49
Asynchronous Page-Mode Read........................................................................................ 51
Synchronous Burst-Mode Read (Code Segment) .............................................................. 52
Burst Suspend .................................................................................................................... 52
Read Array Command (0xFF) ............................................................................................ 53
Read Status Register Command (0x70)............................................................................. 53
Clear Status Register Command (0x50)............................................................................. 55
Read Flash Device Identifier Command (0x90).................................................................. 55
CFI Query Command (0x98) .............................................................................................. 57
Word Program Setup Command (0x40) ............................................................................. 58
11.1.1 Factory Word Programming................................................................................... 59
Buffered Program Setup Command (0xE8)........................................................................ 60
Buffered Program Confirm Command (0xD0) .................................................................... 60
Buffered EFP Setup Command (0x80) ............................................................................... 60
Buffered EFP Confirm Command (0xD0) ........................................................................... 61
11.5.1 Buffered EFP Setup Phase.................................................................................... 62
Buffered EFP Program/Verify Phase .................................................................................. 62
11.6.1 Buffered EFP Exit Phase ....................................................................................... 62
Block Erase Setup Command (0x20) ................................................................................. 63
Block Erase Confirm Command (0xD0).............................................................................. 63
Erase Suspend Command (0xB0) ...................................................................................... 64
Program Suspend Command (0xB0).................................................................................. 64
Program Resume Command (0xD0) .................................................................................. 65
Erase Resume Command (0xD0)....................................................................................... 65
Block Locking During Erase Suspend ................................................................................ 66
14.1.1 F-WP# Lock-Down Control .................................................................................... 67
Lock Block Setup Command (0x60) ................................................................................... 68
Unlock Block Command (0xD0).......................................................................................... 68
Lock-Down Block Command (0x2F) ................................................................................... 68
Reading the Protection Registers ....................................................................................... 69
Program Protection Register Setup Command (0xC0)....................................................... 70
15.2.1 Locking the Protection Registers ........................................................................... 70
Read Mode Bit- RCR.15 ..................................................................................................... 73
10.0 Read Operations
.................................................................................................................... 51
11.0 Program Operations
............................................................................................................. 58
12.0 Erase Operations
................................................................................................................... 63
12.1
12.2
13.1
13.2
13.3
13.4
14.1
14.2
14.3
14.4
15.1
15.2
13.0 Suspend and Resume Operations
................................................................................. 64
14.0 Block Locking and Unlocking Operations
.................................................................. 66
15.0 Protection Register Operation (Code Die)
.................................................................. 69
16.0 Configuration Operations
.................................................................................................. 71
16.1
4
Datasheet
Contents
Latency Count Bit - RCR[13:11] .........................................................................................73
WAIT Polarity Bit - RCR.10.................................................................................................74
16.3.1 WAIT Signal Function ............................................................................................75
16.4 Data Hold Bit - RCR.9.........................................................................................................76
16.5 WAIT Delay Bit - RCR.8 .....................................................................................................76
16.6 Burst Sequence Bit - RCR.7 ...............................................................................................77
16.7 Clock Edge Bit - RCR.6 ......................................................................................................78
16.8 Burst Wrap Bit - RCR.3.......................................................................................................78
16.9 Burst Length Bit - RCR[2:0] ................................................................................................78
16.10 Set Read Configuration Register Command (0x60) ...........................................................78
16.11 Write Read Configuration Register Command (0x03) ........................................................78
16.2
16.3
17.0 Dual Operation Considerations
.......................................................................................79
17.1
17.2
17.3
17.4
Consecutive Back-to-Back Bus Cycle Operations ..............................................................79
Read during a Buffered Program Operation .......................................................................81
Simultaneous Operation Restrictions .................................................................................81
Simultaneous Operation Details .........................................................................................82
17.4.1 Concurrent Operations Power Considerations ......................................................83
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix F
Appendix G
Write State Machine (WSM) for Code Segment
......................................84
Write State Machine (WSM) for Data Segment
.......................................85
Flowcharts
.............................................................................................................86
Common Flash Interface (CFI) for Code Segment
................................94
Common Flash Interface (CFI) for Data Segment
................................ 105
Additional Information
.................................................................................... 110
Ordering Information
....................................................................................... 111
Datasheet
5
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