DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3799
5300 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3799 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD3799 has 3 rows of 5300 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. Therefore,
it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell
• Line spacing
• Color filter
• Resolution
: 5300 pixels
×
3
: 28
µ
m (4 lines) Red line-Green line, Green line-Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•hour)
: 24 dot/mm A4 (210
×
297 mm) size (shorter side)
600 dpi US letter (8.5”
×
11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Power supply
: 4 MHz MAX.
: +12 V
Clamp pulse generation circuit
Voltage amplifiers
• Photocell's pitch : 7
µ
m
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 32-pin plastic DIP (400 mil)
µ
PD3799CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14083EJ1V0DS00 (1st edition)
Date published April 1999 N CP(K)
Printed in Japan
©
1999
µ
PD3799
BLOCK DIAGRAM
V
OD
30
GND
2
GND
11
φ
2
25
φ
1
24
S5299
······
Photocell
(Blue)
S5300
D14
D64
D65
D66
D67
S1
S2
Transfer gate
V
OUT
1
31
(Blue)
D14
CCD analog shift register
S5299
S5300
23
φ
TG1
(Blue)
······
Photocell
(Green)
D64
D65
D66
D67
S1
S2
V
OUT
2
(Green) 32
D14
Transfer gate
CCD analog shift register
S5299
S5300
22
φ
TG2
(Green)
······
Photocell
(Red)
D64
D65
D66
D67
S1
S2
Transfer gate
V
OUT
3
(Red)
1
CCD analog shift register
10
φ
TG3
(Red)
Clamp pulse
generator
3
8
9
φ
RB
φ
2
φ
1
2
DATA SHEET S14083EJ1V0DS00
µ
PD3799
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (400 mil)
•
µ
PD3799CY
Output signal 3 (Red)
V
OUT
3
1
32
V
OUT
2
Output signal 2 (Green)
Ground
GND
2
1
1
1
31
V
OUT
1
Output signal 1 (Blue)
Reset gate clock
φ
RB
3
30
V
OD
Output drain voltage
No connection
NC
4
29
NC
No connection
No connection
NC
5
28
NC
No connection
Internal connection
IC
6
27
IC
Internal connection
Internal connection
IC
7
26
IC
Internal connection
Shift register clock 2
φ
2
8
Green
Blue
Red
25
φ
2
Shift register clock 2
Shift register clock 1
φ
1
9
24
φ
1
Shift register clock 1
Transfer gate clock 3
(for Red)
Ground
φ
TG3
10
23
φ
TG1
Transfer gate clock 1
(for Blue)
Transfer gate clock 2
(for Green)
Internal connection
GND
11
22
φ
TG2
Internal connection
IC
12
21
IC
Internal connection
IC
13
20
IC
Internal connection
No connection
NC
14
19
NC
No connection
5300
5300
5300
No connection
NC
15
18
NC
No connection
No connection
NC
16
17
NC
No connection
Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
DATA SHEET S14083EJ1V0DS00
3
µ
PD3799
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
7
µ
m
4
µ
m
3
µ
m
Blue photocell array
4 lines
(28
µ
m)
7
µ
m
7
µ
m
Channel stopper
Green photocell array
4 lines
(28
µ
m)
7
µ
m
Aluminum
shield
Red photocell array
4
DATA SHEET S14083EJ1V0DS00
µ
PD3799
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
V
φ
RB
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–25 to +60
–40 to +70
Unit
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
V
φ
1L
, V
φ
2L
V
φ
RBH
V
φ
RBL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
f
φ
RB
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
V
φ
1H
Note
0
1.0
MAX.
12.6
5.5
+0.5
5.5
+0.5
V
φ
1H
Note
+0.5
4.0
Unit
V
V
V
V
V
V
V
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
),
Image lag can increase.
DATA SHEET S14083EJ1V0DS00
5
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