DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3788
7300 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3788 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The
µ
PD3788 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Moreover, the spectral response characteristics of the
µ
PD3788 is modified from the previous device
µ
PD3728 to be
suitable for Xe-lamp. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
• Valid photocell
• Photocell pitch
• Photocell size
• Line spacing
• Color filter
• Resolution
• Data rate
• Output type
• Power supply
• On-chip circuits
: 7300 pixels
×
3
: 10
µ
m
: 10
×
10
µ
m
2
: 40
µ
m (4 lines) Red line-Green line, Green line-Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•hour)
: 24 dot/mm (600 dpi) A3 (297
×
420 mm) size (shorter side)
: 40 MHz MAX. (20 MHz/1 output)
: 2 outputs in phase/color
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
• Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
µ
PD3788D
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14664EJ1V0DS00(1st edition)
Date published June 2000 N CP(K)
Printed in Japan
©
2000
µ
PD3788
COMPARISON CHART
Item
ABSOLUTE MAXIMUM
RATINGS
Shift register clock voltage (V)
Reset gate clock voltage (V)
Reset feed-through level clamp clock voltage (V)
Transfer gate clock voltage (V)
ELECTRICAL
CHARACTERISTICS
Saturation exposure (Ix·s)
Red
Green
Blue
Response (V/Ix·s)
Red
TYP.
TYP.
TYP.
MIN.
TYP.
MAX.
Green
MIN.
TYP.
MAX.
Blue
MIN.
TYP.
MAX.
Response peak (nm)
Red
Green
Blue
Random noise test conditions
TIMING CHART
t3 (ns)
t7 (ns)
t10 (ns)
t
CP
(ns)
MIN.
MIN.
MIN.
MIN.
TYP.
STANDARD
CHARACTERISTIC
CURVES
TOTAL SPECTRAL
RESPONSE CHARACTERISTICS
TYP.
TYP.
TYP.
µ
PD3788
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
0.36
0.37
0.80
3.85
5.5
7.15
3.78
5.4
7.02
1.75
2.5
3.25
645
540
445
t
cp
= 20 ns
17
17
–20
5
150
modified
µ
PD3728
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
0.35
0.39
0.31
3.9
5.6
7.3
3.6
5.1
6.6
4.5
6.4
8.3
630
540
460
t7 = 150 ns
20
20
–10
–
–
–
2
Data Sheet S14664EJ1V0DS00
µ
PD3788
BLOCK DIAGRAM
φ
CLB
30
φ
1L
29
φ
20
28
GND
16
φ
1
23
φ
2
24
GND
31
V
OUT
2
(Blue, even)
32
D128
CCD analog shift register
Transfer gate
S7299
S7300
D129
D27
GND
33
.....
S1
S2
Photocell
(Blue)
.....
D134
22
φ
TG1
(Blue)
V
OUT
1
(Blue, odd)
GND
34
35
Transfer gate
CCD analog shift register
V
OUT
3
36
(Green, odd)
D128
D27
CCD analog shift register
Transfer gate
S7299
S7300
D129
S1
S2
.....
Photocell
(Green)
.....
D134
21
φ
TG2
(Green)
V
OUT
4
1
(Green, even)
GND
V
OUT
6
(Red, even)
2
3
D128
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
S7299
S7300
D129
D27
S1
S2
GND
4
.....
Photocell
(Red)
.....
D134
15
φ
TG3
(Red)
V
OUT
5
(Red, odd)
5
Transfer gate
CCD analog shift register
GND
6
7
V
OD
8
9
13
14
φ
RB
φ
10
φ
1
φ
2
Data Sheet S14664EJ1V0DS00
3
µ
PD3788
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
•
µ
PD3788D
Output signal 4 (Green, even) V
OUT
4 1
Ground
GND 2
1
1
1
36 V
OUT
3
35 GND
34 V
OUT
1
33 GND
32 V
OUT
2
31 GND
30
φ
CLB
29
φ
1L
28
φ
20
Green
Output signal 3 (Green, odd)
Ground
Output signal 1 (Blue, odd)
Ground
Output signal 2 (Blue, even)
Ground
Reset feed-through level
clamp clock
Last stage shift register clock 1
Shift register clock 20
Output signal 6 (Red, even) V
OUT
6 3
Ground
GND 4
Output signal 5 (Red, odd) V
OUT
5 5
Ground
Output drain voltage
Reset gate clock
Shift register clock 10
GND 6
V
OD
7
φ
RB 8
φ
10 9
Blue
Red
No connection
No connection
No connection
Shift register clock 1
Shift register clock 2
NC 10
NC 11
NC 12
27 NC
26 NC
25 NC
24
φ
2
23
φ
1
22
φ
TG1
7300
7300
7300
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock 1 (for Blue)
Transfer gate clock 2 (for Green)
No connection
No connection
φ
1 13
φ
2 14
Transfer gate clock 3 (for Red)
φ
TG3 15
Ground
No connection
No connection
GND 16
NC 17
NC 18
21
φ
TG2
20 NC
19 NC
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
10
µ
m
7
µ
m
3
µ
m
Blue photocell array
4 lines
(40
µ
m)
10
µ
m
Channel stopper
10
µ
m
Green photocell array
4 lines
(40
µ
m)
10
µ
m
Aluminum
shield
Red photocell array
4
Data Sheet S14664EJ1V0DS00
µ
PD3788
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
1L
, V
φ
10
, V
φ
2
, V
φ
20
V
φ
RB
V
φ
CLB
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–25 to +60
–40 to +100
Unit
V
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Note
V
OD
V
φ
1H
, V
φ
1LH
, V
φ
10H
, V
φ
2H
, V
φ
20H
V
φ
1L
, V
φ
1LL
, V
φ
10L
, V
φ
2L
, V
φ
20L
V
φ
RBH
V
φ
RBL
V
φ
CLBH
V
φ
CLBL
V
φ
TG1H
to V
φ
TG3H
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
TYP.
12.0
5.0
0
5.0
0
5.0
0
V
φ
1H
(V
φ
10H
)
Transfer gate clock low level
Data rate
V
φ
TG1L
to V
φ
TG3L
2f
φ
RB
–0.3
–
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
V
φ
1H
(V
φ
10H
)
+0.5
40
V
MHz
Unit
V
V
V
V
V
V
V
V
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
(V
φ
10H
)),
Image lag can increase.
Remark
Pin 9 (
φ
10) and pin 28 (
φ
20) should be open to decrease the influence of input clock noise to output signal
waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
Data Sheet S14664EJ1V0DS00
5
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