DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3747
7400 PIXELS CCD LINEAR IMAGE SENSOR
The
µ
PD3747 is a high-speed and high sensitive CCD (Charge Coupled Device) linear image sensor which changes
optical images to electrical signal.
The
µ
PD3747 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the
photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits
and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
•
Valid photocell
•
Photocell pitch
•
Photocell size
•
Resolution
•
Data rate
•
Output type
•
High sensitivity
•
Low image lag
•
Power supply
•
On-chip circuits
:
: 7400 pixels
: 4.7
µ
m
: 4.7
×
4.7
µ
m
2
: 24 dot/mm (600 dpi) A3 (297
×
420 mm) size (shorter side)
: 44 MHz MAX. (22 MHz/1 output)
: 2 outputs in phase
: 19.0 V/lx•s TYP (Light source: Daylight color fluorescent lamp)
.
: 1 % MAX.
: +12 V
•
Drive clock level : CMOS output under 5 V operation
: Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
µ
PD3747D
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14892EJ1V0DS00 (1st edition)
Date Published June 2000 NS CP (K)
Printed in Japan
©
2000
S1
S2
D33
D134
D135
S7399
Transfer gate
CCD analog shift register
Data Sheet S14892EJ1V0DS00
V
OUT
1 (Odd)
1
2
4
5
S7400
9
10
V
OD
φ
R
φ
2L
φ
1
φ
2
D140
2
φ
2L
18
14
13
BLOCK DIAGRAM
GND
GND
φ
CP
φ
2
φ
1
21
11
20
V
OUT
2 (Even)
CCD analog shift register
Transfer gate
22
···
Photocell
···
12
φ
TG
µ
PD3747
µ
PD3747
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (10.16 mm (400))
•
µ
PD3747D
Output signal 1 (Odd)
Output drain voltage
No connection
Reset gate clock
Last stage shift register clock 2
No connection
No connection
No connection
Shift register clock 1
Shift register clock 2
Ground
V
OUT
1
V
OD
NC
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
OUT
2
GND
Output signal 2 (Even)
Ground
Reset feed-through level clamp clock
No connection
Last stage shift register clock 2
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock
φ
CP
NC
φ
R
φ
2L
NC
NC
NC
φ
2L
NC
NC
NC
φ
1
φ
2
GND
φ
2
φ
1
φ
TG
PHOTOCELL STRUCTURE DIAGRAM
3.2
µ
m
1.5
µ
m
4.7
µ
m
Channel stopper
Aluminum
shield
Data Sheet S14892EJ1V0DS00
3
µ
PD3747
ABSOLUTE MAXIMUM RATINGS (T
A
= +25°C)
°
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
, V
φ
2L
V
φ
R
V
φ
CP
V
φ
TG
T
A
T
stg
Symbol
Ratings
−0.3
to +14
−0.3
to +8
−0.3
to +8
−0.3
to +8
−0.3
to +8
−25
to +55
−40
to +100
Unit
V
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25°C)
°
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
, V
φ
2LH
V
φ
1L
, V
φ
2L
, V
φ
2LL
V
φ
RH
V
φ
RL
V
φ
CPH
V
φ
CPL
V
φ
TGH
V
φ
TGL
2f
φ
R
Symbol
MIN.
11.4
4.5
−0.3
4.5
−0.3
4.5
−0.3
4.5
−0.3
1
TYP.
12.0
5.0
0
5.0
0
5.0
0
5.0
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
5.5
+0.5
44
Unit
V
V
V
V
V
V
V
V
V
MHz
4
Data Sheet S14892EJ1V0DS00
µ
PD3747
ELECTRICAL CHARACTERISTICS
T
A
= +25°C, V
OD
= 12 V, f
φ
R
= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
Image lag
Offset level
Note 1
Note 2
Symbol
V
sat
SE
PRNU
ADS
DSNU
P
W
Z
O
R
F
IL
V
OS
t
d
RI
TTE
Test Conditions
MIN.
1.5
−
−
−
−
−
−
TYP.
2.0
0.10
5
0.5
8.0
350
0.2
19.0
0.5
4.7
14
1.0
98
550
250
1000
+300
2.0
8.0
8.0
MAX.
−
−
10
3.0
14.0
600
0.3
24.7
1.0
5.7
−
4.0
−
−
−
−
+900
−
−
−
Unit
V
lx•s
%
mV
mV
mW
kΩ
V/lx•s
%
V
ns
%
%
nm
times
times
mV
mV
mV
mV
Daylight color fluorescent lamp
V
OUT
= 500 mV
Light shielding
Light shielding
Daylight color fluorescent lamp
V
OUT
= 500 mV
13.3
−
3.7
−
0
94
−
Output fall delay time
Register imbalance
V
OUT
= 500 mV
V
OUT
= 500 mV
V
OUT
= 1 V, data rate = 44 MHz
Total transfer efficiency
Response peak
Dynamic range
Note 1
DR1
DR2
V
sat
/DSNU
V
sat
/
σ
bit
Light shielding
Light shielding, bit clamp mode
Light shielding, line clamp mode
V
OUT
= 500 mV, bit clamp mode
−
−
−300
−
−
−
Reset feed-through noise
Random noise
RFTN
σ
bit
σ
line
σ
shot
Shot noise
Notes 1.
Refer to
TIMING CHART 2, 3.
.
2.
When the fall time of
φ
2L (t2’) is the TYP value (refer to
TIMING CHART 2, 3).
Note that V
OUT
1 and V
OUT
2 are
the outputs of the two steps of emitter-follower shown in
APPLICATION CIRCUIT EXAMPLE.
Data Sheet S14892EJ1V0DS00
5
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