DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3729
5000 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3729 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The
µ
PD3729 has 3 rows of 5000 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 5000 pixels separately in odd and even pixels.
Therefore, it is suitable for 400 dpi/A3 high-speed color digital copiers and so on.
FEATURES
• Valid photocell
• Line spacing
• Color filter
• Resolution
• Data rate
• Output type
• Power supply
• On-chip circuits
: 5000 pixels
×
3
: 40
µ
m (4 lines) Red line-Green line, Green line-Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•hour)
: 16 dot/mm (400 dpi) A3 (297
×
420 mm) size (shorter side)
: 30 MHz MAX. (15 MHz/1 output)
: 2 outputs in phase/color
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
• Photocell's pitch : 10
µ
m
• Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 24-pin ceramic DIP (400 mil)
µ
PD3729D
The information in this document is subject to change without notice.
Document No. S12883EJ1V0DS00(1st edition)
Date published November 1998 N CP(K)
Printed in Japan
©
1998
µ
PD3729
BLOCK DIAGRAM
φ
CLB
20
φ
1L
19
V
OD
5
GND GND GND
4
12
21
φ
1
15
φ
2
16
V
OUT
2
(Blue, even)
22
D128
CCD analog shift register
Transfer gate
S4999
S5000
D129
D27
.....
S1
S2
Photocell
(Blue)
.....
D134
14
φ
TG1
(Blue)
V
OUT
1
(Blue, odd)
23
Transfer gate
CCD analog shift register
V
OUT
3
24
(Green, odd)
D128
D27
CCD analog shift register
Transfer gate
S4999
S5000
D129
S1
S2
.....
Photocell
(Green)
.....
D134
13
φ
TG2
(Green)
V
OUT
4
1
(Green, even)
Transfer gate
CCD analog shift register
V
OUT
6
(Red, even)
2
D128
CCD analog shift register
Transfer gate
S4999
S5000
D129
D27
S1
S2
.....
Photocell
(Red)
.....
D134
11
φ
TG3
(Red)
V
OUT
5
(Red, odd)
3
Transfer gate
CCD analog shift register
6
9
10
φ
RB
φ
1
φ
2
2
µ
PD3729
PIN CONFIGURATION (Top View)
CCD linear image sensor 24-pin ceramic DIP (400 mil)
•
µ
PD3729D
Output signal 4 (Green, even)
V
OUT
4
1
24
V
OUT
3 Output signal 3 (Green, odd)
Output signal 6 (Red, even)
V
OUT
6
2
23
V
OUT
1 Output signal 1 (Blue, odd)
1
1
1
Output signal 5 (Red, odd)
V
OUT
5
3
22
V
OUT
2 Output signal 2 (Blue, even)
Ground
GND
4
21
GND
Ground
Output drain voltage
V
OD
5
20
φ
CLB Reset feed-through level
clamp clock
φ
1L
Last stage shift register clock 1
Reset gate clock
φ
RB
6
19
Green
No connection
NC
7
Blue
Red
18
NC
No connection
No connection
NC
8
17
NC
No connection
Shift register clock 1
φ
1
9
16
φ
2
Shift register clock 2
Shift register clock 2
φ
2
10
15
φ
1
Shift register clock 1
5000
5000
5000
Transfer gate clock 3 (for Red)
φ
TG3
11
14
φ
TG1 Transfer gate clock 1 (for Blue)
Ground
GND
12
13
φ
TG2 Transfer gate clock 2 (for Green)
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
10
µ
m
Blue photocell array
4 lines
(40
µ
m)
10
µ
m
Green photocell array
4 lines
(40
µ
m)
10
µ
m
Red photocell array
7
µ
m
3
µ
m
10
µ
m
Channel stopper
Aluminum
shield
3
µ
PD3729
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
1L
, V
φ
2
V
φ
RB
V
φ
CLB
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +70
–40 to +100
Unit
V
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
1LH
, V
φ
2H
V
φ
1L
, V
φ
1LL
, V
φ
2L
V
φ
RBH
V
φ
RBL
V
φ
CLBH
V
φ
CLBL
V
φ
TG1H
to V
φ
TG3H
V
φ
TG1L
to V
φ
TG3L
2f
φ
RB
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
5.0
0
V
φ
1H
Note
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
V
φ
1H
Note
+0.5
30
Unit
V
V
V
V
V
V
V
V
V
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
), Image
lag can increase.
4
µ
PD3729
ELECTRICAL CHARACTERISTICS
T
A
= +25
°C,
V
OD
= 12 V, f
φ
RB
= 1 MHz, data rate = 2 MHz, storage time = 10 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 V
p-p
Parameter
Saturation voltage
Saturation exposure
Red
Green
Blue
Photo response non-uniformity
Average dark signal
Note 1
Symbol
V
sat
SER
SEG
SEB
PRNU
ADS1
ADS2
Dark signal non-uniformity
Note 1
DSNU1
DSNU2
Power consumption
Output impedance
Response
Red
Green
Blue
Image lag
Note 1
P
W
Z
O
R
R
R
G
R
B
IL1
IL2
Offset level
Note 2
Output fall delay time
Note 3
Register imbalance
Total transfer efficiency
V
OS
t
d
RI
TTE
V
OUT
= 1 V
V
OUT
= 1 V
V
OUT
= 1 V,
data rate = 30 MHz
Response peak
Red
Green
Blue
Dynamic range
Note 1
DR11
DR12
DR21
DR22
Reset feed-through noise
Note 2
Random noise
Note 1
RFTN
σ1
σ2
V
sat
/DSNU1
V
sat
/DSNU2
V
sat
/σ1
V
sat
/σ2
Light shielding
Light shielding
–500
–
–
630
540
460
1000
2000
2000
4000
+200
1.0
0.5
+500
–
–
nm
nm
nm
times
times
times
times
mV
mV
mV
0
95
98
4.0
V
OUT
= 1 V
4.3
3.8
4.7
Light shielding
V
OUT
= 1 V
Light shielding
Test Conditions
MIN.
1.5
TYP.
2.0
0.32
0.37
0.29
6
1.0
0.5
2.0
1.0
500
0.3
6.2
5.4
6.8
2.0
1.0
5.0
25
4.0
18
5.0
5.0
5.0
5.0
700
0.5
8.1
7.0
8.9
5.0
5.0
6.0
MAX.
–
Unit
V
lx
•
s
lx
•
s
lx
•
s
%
mV
mV
mV
mV
mW
kΩ
V/lx
•
s
V/lx
•
s
V/lx
•
s
%
%
V
ns
%
%
Notes 1.
ADS1, DSNU1, IL1, DR11 and DR21 show the specification of V
OUT
1 and V
OUT
2.
ADS2, DSNU2, IL2, DR12 and DR22 show the specification of V
OUT
3 to V
OUT
6.
2.
Refer to
TIMING CHART 2.
3.
When the fall time of
φ
1L (t2’) is the TYP. value (refer to
TIMING CHART 2).
5
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