DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3728DZ
7300 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The
µ
PD3728DZ is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The
µ
PD3728DZ has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
•
Valid photocell
•
Photocell pitch
•
Line spacing
•
Color filter
•
Resolution
•
Data rate
•
Output type
•
Power supply
•
On-chip circuits
: 7300 pixels
×
3
: 10
µ
m
: 40
µ
m (4 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10 lx•hour)
: 24 dot/mm A3 (297
×
420 mm) size (shorter side)
: 40 MHz MAX. (20 MHz/1 output)
: 2 outputs in phase/color
: +12 V
: Reset feed-through level clamp circuits
Voltage amplifiers
7
•
Drive clock level : CMOS output under 5 V operation
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
µ
PD3728DZ
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S15417EJ2V0DS00 (2nd edition)
Date Published October 2002 NS CP (K)
Printed in Japan
The mark
shows major revised points.
2001
µ
PD3728DZ
BLOCK DIAGRAM
φ
CLB
φ
1L
φ
20
GND
16
φ
1
φ
2
30
29
28
23
24
GND
31
V
OUT
2
(Blue, even)
32
D128
CCD analog shift register
Transfer gate
S7299
S7300
D129
D27
GND
33
.....
S1
S2
Photocell
(Blue)
.....
D134
22
φ
TG1
(Blue)
V
OUT
1
(Blue, odd)
GND
34
35
Transfer gate
CCD analog shift register
V
OUT
3
36
(Green, odd)
D128
D27
CCD analog shift register
Transfer gate
S7299
S7300
D129
S1
S2
D134
.....
Photocell
(Green)
.....
21
φ
TG2
(Green)
V
OUT
4
1
(Green, even)
GND
V
OUT
6
(Red, even)
2
3
D128
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
D129
S1
S2
D134
D27
GND
4
.....
Photocell
(Red)
S7299
S7300
.....
15
φ
TG3
(Red)
V
OUT
5
(Red, odd)
5
Transfer gate
CCD analog shift register
GND
6
7
V
OD
8
φ
RB
9
φ
10
13
φ
1
14
φ
2
2
Data Sheet S15417EJ2V0DS
µ
PD3728DZ
PIN CONFIGURATION (Top View)
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
•
µ
PD3728DZ
Output signal 4 (Green, even) V
OUT
4
Ground
GND
1
2
1
1
1
36
35
34
33
32
31
30
29
28
Green
V
OUT
3
GND
V
OUT
1
GND
V
OUT
2
GND
φ
CLB
φ
1L
φ
20
Output signal 3 (Green, odd)
Ground
Output signal 1 (Blue, odd)
Ground
Output signal 2 (Blue, even)
Ground
Reset feed-through level clamp clock
Last stage shift register clock 1
Shift register clock 20
Output signal 6 (Red, even) V
OUT
6
Ground
GND
3
4
5
6
7
8
9
Output signal 5 (Red, odd) V
OUT
5
Ground
Output drain voltage
Reset gate clock
Shift register clock 10
GND
V
OD
φ
RB
φ
10
No connection
No connection
No connection
Shift register clock 1
Shift register clock 2
NC
NC
NC
φ
1
φ
2
Blue
Red
10
11
12
13
14
15
7300
7300
7300
27
26
25
24
23
22
21
20
19
NC
NC
NC
φ
2
φ
1
φ
TG1
φ
TG2
No connection
No connection
No connection
Shift register clock 2
Shift register clock 1
Transfer gate clock 1 (for Blue)
Transfer gate clock 2 (for Green)
No connection
No connection
Transfer gate clock 3 (for Red)
φ
TG3
Ground
No connection
No connection
GND
NC
NC
16
17
18
NC
NC
Caution
Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
10
µ
m
Blue photocell array
4 lines
(40
µ
m)
7
µ
m
3
µ
m
10
µ
m
Channel stopper
10
µ
m
Green photocell array
4 lines
(40
µ
m)
Aluminum
shield
10
µ
m
Red photocell array
Data Sheet S15417EJ2V0DS
3
µ
PD3728DZ
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
25°C)
°
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Note
Symbol
V
OD
V
φ
1
, V
φ
1L
, V
φ
10
, V
φ
2
, V
φ
20
V
φ
RB
V
φ
CLB
V
φ
TG1
to V
φ
TG3
T
A
T
stg
Ratings
−0.3
to
+15
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−0.3
to
+8
−25
to
+60
−40
to
+100
Unit
V
V
V
V
V
°C
°C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
25°C)
°
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
V
OD
V
φ
1H
, V
φ
1LH
, V
φ
10H
, V
φ
2H
, V
φ
20H
V
φ
1L
, V
φ
1LL
, V
φ
10L
, V
φ
2L
, V
φ
20L
V
φ
RBH
V
φ
RBL
V
φ
CLBH
V
φ
CLBL
V
φ
TG1H
to V
φ
TG3H
Symbol
Min.
11.4
4.5
−0.3
4.5
−0.3
4.5
−0.3
4.5
Typ.
12.0
5.0
0
5.0
0
5.0
0
Note
V
φ
1H
Max.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
Note
V
φ
1H
Unit
V
V
V
V
V
V
V
V
(V
φ
10H
)
Transfer gate clock low level
Data rate
V
φ
TG1L
to V
φ
TG3L
2f
φ
RB
−0.3
−
0
2
(V
φ
10H
)
+0.5
40
V
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
(V
φ
10H
)), Image lag can increase.
Remark
Pin 9 (
φ
10) and pin 28 (
φ
20) should be open to decrease the influence of input clock noise to output
signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
4
Data Sheet S15417EJ2V0DS
µ
PD3728DZ
ELECTRICAL CHARACTERISTICS
T
A
=
+25°C,
V
OD
= 12 V, f
φ
RB
= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V
p-p
,
light source: 3200 K halogen lamp
+C-500S
(infrared cut filter, t = 1 mm)+HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Red
Green
Blue
Photo response non-uniformity
Average dark signal
Note1
Symbol
V
sat
SER
SEG
SEB
PRNU
ADS1
ADS2
Note1
Test Conditions
Min.
1.5
−
−
−
−
−
−
−
−
−
−
3.9
3.6
4.5
Typ.
2.0
0.35
0.39
0.31
6.0
1.0
0.5
2.0
1.0
600
0.3
5.6
5.1
6.4
2.0
1.0
5.0
20
−
98
630
540
460
1000
2000
2000
4000
+200
1.0
0.5
4.0
2.0
Max.
−
−
−
−
18.0
5.0
5.0
5.0
5.0
800
0.5
7.3
6.6
8.3
5.0
5.0
6.0
−
4.0
−
−
−
−
−
−
−
−
+500
−
−
−
−
Unit
V
lx•s
lx•s
lx•s
%
mV
mV
mV
mV
mW
kΩ
V/lx•s
V/lx•s
V/lx•s
%
%
V
ns
%
%
nm
nm
nm
times
times
times
times
mV
mV
mV
mV
mV
V
OUT
= 1.0 V
Light shielding
Dark signal non-uniformity
DSNU1
DSNU2
Light shielding
Power consumption
Output impedance
Response
Red
Green
Blue
Image lag
Note1
P
W
Z
O
R
R
R
G
R
B
IL1
IL2
V
OUT
= 1.0 V
−
−
4.0
−
0
95
−
−
−
−
−
−
−
−500
−
−
−
−
Offset level
Note2
Note3
V
OS
t
d
RI
TTE
Red
Green
Blue
V
OUT
= 1.0 V
V
OUT
= 1.0 V
V
OUT
= 1.0 V, data rate = 40 MHz
Output fall delay time
Register imbalance
Total transfer efficiency
Response peak
Dynamic range
Note1
DR11
DR12
DR21
DR22
Note2
V
sat
/DSNU1
V
sat
/DSNU2
V
sat
/
σ
bit1
V
sat
/
σ
bit2
Light shielding
Light shielding,
bit clamp mode (t
cp
= 150 ns)
Light shielding,
line clamp mode (t19 = 3
µ
s)
Reset feed-through noise
Random noise
Note1
RFTN
σ
bit1
σ
bit2
σ
line1
σ
line2
Notes 1.
ADS1, DSNU1, IL1, DR11, DR21,
σ
bit1 and
σ
line1 show the specification of V
OUT
1 and V
OUT
2.
ADS2, DSNU2, IL2, DR12, DR22,
σ
bit2 and
σ
line2 show the specification of V
OUT
3 to V
OUT
6.
2.
Refer to
TIMING CHART 2, 5.
3.
When the fall time of
φ
1L (t2’) is the TYP. value (refer to
TIMING CHART 2, 5).
Data Sheet S15417EJ2V0DS
5
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