DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD3720A
2700 PIXELS
×
3 COLOR CCD LINEAR IMAGE SENSOR
The
µ
PD3720A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
µ
PD3720A has 3 rows of 2700 pixels and 3 pairs of 2 rows of 1350-bit charge transferred registers, reset feed-
through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. It is suitable for color image
scanners, color facsimiles and so on.
FEATURES
• Valid photocell
• Line spacing
• Color filter
• Resolution
: 2700 pixels
×
3
: 42
µ
m (4 lines) Red line-Green line, Green line-Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lx•hour)
: 12 dot/mm A4 (210
×
297 mm) size (shorter side)
300 dpi US letter (8.5”
×
11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Power supply
• On-chip circuits
: 3 MHz MAX.
: +12 V
: Reset feed-through level clamp circuits
Clamp pulse generation circuit
Voltage amplifiers
• Pin assign
: Compatible with the
µ
PD3720
• Photocell's pitch : 10.5
µ
m
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (400 mil)
µ
PD3720ACY
The information in this document is subject to change without notice.
Document No. S12035EJ1V0DS00(1st edition)
Date published November 1996 N
Printed in Japan
©
1996
µ
PD3720A
COMPARISON CHART
Item
PIN CONFIGURATION
ELECTRICAL
CHARACTERISTICS
TIMING CHART
Pin 11
Output fall delay time
TYP. (ns)
Output signal waveform
µ
PD3720A
Analog ground
70
µ
PD3720
Digital ground
80
Spike noise reduced
–
BLOCK DIAGRAM
V
OD
19
AGND
2
AGND
11
φ
2L
φ
1
17
14
CCD analog shift register
Transfer gate
S2699
S2700
13
D65
D66
D67
V
OUT
1
(B)
D14
S1
21
S2
........
D64
Photocell
φ
TG1
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
S2699
S2700
D14
D64
D65
D66
12
D67
V
OUT
2
(G)
S1
S2
22
........
Photocell
φ
TG2
Transfer gate
CCD analog shift register
Clamp pulse
generator
CCD analog shift register
Transfer gate
S2699
S2700
10
D65
D66
D67
V
OUT
3
(R)
D14
S1
S2
1
........
D64
Photocell
φ
TG3
Transfer gate
CCD analog shift register
3
φ
RB
4
φ
1L
9
φ
2
2
µ
PD3720A
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP(400 mil)
Output signal 3 (RED)
V
OUT
3
1
22
V
OUT
2
Output signal 2 (GREEN)
Analog ground
AGND
2
1
1
1
21
V
OUT
1
Output signal 1 (BLUE)
Reset gate clock
φ
RB
3
20
NC
No connection
Last stage shift register clock 1
φ
1L
4
19
V
OD
Output drain voltage
No connection
NC
5
18
NC
No connection
No connection
NC
6
G
R
B
17
φ
2L
Last stage shift register clock 2
No connection
NC
7
16
NC
No connection
No connection
NC
8
15
NC
No connection
Shift register clock 2
φ
2
9
14
φ
1
Shift register clock 1
2700
2700
2700
Transfer gate clock 3
φ
TG3
10
13
φ
TG1
Transfer gate clock 1
Analog ground
AGND
11
12
φ
TG2
Transfer gate clock 2
PHOTOCELL STRUCTURE DIAGRAM
7.5
µ
m
10.5
µ
m
3
µ
m
Channel stopper
Aluminum
shield
3
µ
PD3720A
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
V
OD
V
φ
1
, V
φ
2
, V
φ
1L
, V
φ
2L
V
φ
RB
V
φ
TG1
– V
φ
TG3
T
A
T
stg
Symbol
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +60
–40 to +70
Unit
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Output drain voltage
Shift register clock signal high level
Shift register clock signal low level
Reset gate clock high level
Reset gate clock low level
Transfer gate clock high level
Transfer gate clock low level
Data rate
V
OD
V
φ
1H
, V
φ
2H
, V
φ
1LH
, V
φ
2LH
V
φ
1L
, V
φ
2L
, V
φ
1LL
, V
φ
2LL
V
φ
RBH
V
φ
RBL
V
φ
TG1H
– V
φ
TG3H
V
φ
TG1L
– V
φ
TG3L
f
φ
RB
Symbol
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
5.0
0
1
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
3
Unit
V
V
V
V
V
V
V
MHz
4
µ
PD3720A
ELECTRICAL CHARACTERISTICS
T
A
= +25
°C,
V
OD
= 12 V, f
φ
RB
= 1 MHz, data rate = 1 MHz, storage time = 5 ms,
light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm), input signal clock = 5 V
p-p
Parameter
Saturation voltage
Saturation exposure
Red
Green
Blue
Photo response non-uniformity
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
Red
Green
Blue
Image lag
Offset level
Note1
Output fall delay time
Note2
Total transfer efficiency
Symbol
V
sat
SER
SEG
SEB
PRNU
ADS
DSNU
P
W
Z
O
R
R
R
G
R
B
IL
V
OS
t
d
TTE
Test Conditions
MIN.
2.0
TYP.
3.0
0.15
0.16
0.27
MAX.
–
Unit
V
lx•s
lx•s
lx•s
V
OUT
= 1 V
Light shielding
Light shielding
6
0.5
1.5
400
0.5
14.14
12.95
7.77
20.20
18.50
11.10
2
3
4.5
70
92
98
20
2.5
8.0
600
1
26.26
24.05
14.43
10
6.6
%
mV
mV
mW
kΩ
V/lx•s
V/lx•s
V/lx•s
%
V
ns
%
V
OUT
= 1 V
V
OUT
= 1 V
V
OUT
= 1 V,
data rate = 3 MHz
V
OUT
= 1 V
Register imbalance
Response peak
Red
Green
Blue
Dynamic range
RI
0
1.0
630
540
460
4.0
%
nm
nm
nm
times
times
DR1
DR2
V
sat
/DSNU
V
sat
/σ
Light shielding
Light shielding
–1000
–
2000
3000
–300
1.0
+300
–
Reset feed-through noise
Note1
Random noise
RFTN
σ
mV
mV
Notes 1.
Refer to
TIMING CHART2.
2.
When each fall delay time of
φ
1L and
φ
2L (t2´, t1´) is the TYP. value (refer to
TIMING CHART 2).
5
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