DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD29F064115-X
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY
4M-WORD BY 16-BIT (WORD MODE)
PAGE MODE
Description
The
µ
PD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can
be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire
chip can be erased. Memory organization is 4,194,304 words
×
16 bits, so that the memory can be programmed in
word units.
µ
PD29F064115-X can be read high speed with page mode.
The
µ
PD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided
into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three
banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits.
Input /output voltage is supplied to 2.7 to 3.3 V.
Because the
µ
PD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In
addition, program code that controls the flash memory can be also stored, and the program code can be programmed
or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which
can be erased in 4K words units.
Once a program or erase command sequence has been executed, an automatic program or automatic erase
function internally executes program or erase and verification automatically. The programming time is about 0.5
seconds per sector. The erase time is less than 1 second per sector.
Because the
µ
PD29F064115-X can be electrically erased or programmed by writing an instruction, data can be
reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of
applications.
This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
Features
•
Four bank organization enabling simultaneous execution of program / erase and read
•
High-speed read with page mode
•
Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
•
Memory organization : 4,194,304 words
×
16 bits
•
Sector organization : 142 sectors (4K words
×
16 sectors, 32K words
×
126 sectors)
The boot sector is located at the highest address (sector) and the lowest address (sector)
•
3-state output
•
Automatic program
•
Program suspend / resume
•
Unlock bypass program
•
Automatic erase
•
Chip erase
•
Sector erase (sectors can be combined freely)
•
Erase suspend / resume
•
Program / Erase completion detection
•
Detection through data polling and toggle bits
•
Detection through RY (/BY) pin
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M16062EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark
#
shows major revised points.
©
2002
µ
PD29F064115-X
•
Sector group protection
•
Any sector group can be protected
•
Any protected sector group can be temporary unprotected
•
Any sector group can be unprotected
•
Sectors can be used for boot application
•
Hardware reset and standby using /RESET pin
•
Automatic sleep mode
•
Boot block sector protect by /WP (ACC) pin
•
Extra One Time Protect Sector provided
µ
PD29F064115
Access time
ns (MAX.)
Operating supply voltage V
Chip
V
CC
-DB80X, -DB85X
-EB80X
Note
, -EB85X, -EB90X
80, 85
80
Note
, 85, 90
1.95
±
0.15
1.8
±
0.15
I/O
V
CC
Q
3.0
±
0.3
Power supply current (MAX.)
At active
Read
20
15
mA
At standby
µ
A
Program / Erase
35
25
25
Note
Under Development
•
Program / erase time
•
Program : 11.0
µ
s / word (TYP.)
•
Sector erase :
Program / erase cycle : 100,000 cycle
0.15 s (TYP.) (4K words sector), 0.5 s (TYP.) (32K words sector)
Program / erase cycle : 300,000 cycle
0.5 s (TYP.) (4K words sector), 0.7 s (TYP.) (32K words sector)
•
Program / erase cycle : 300,000 cycle (MIN.)
Ordering Information
Part number
Access time
ns (MAX.)
Operating supply voltage V
Chip
V
CC
I/O
V
CC
Q
3.0
±
0.3
Operating
temperature
°C
−25
to +85
48-pin PLASTIC TSOP (I) (12
×
20)
(Normal bent)
63-pin TAPE FBGA (11
×
8)
Package
µ
PD29F064115GZ-DB80X-MJH
µ
PD29F064115GZ-DB85X-MJH
µ
PD29F064115F9-DB80X-CD6
µ
PD29F064115F9-DB85X-CD6
µ
PD29F064115F9-DB80X-CD5
µ
PD29F064115F9-DB85X-CD5
µ
PD29F064115GZ-EB85X-MJH
µ
PD29F064115GZ-EB90X-MJH
µ
PD29F064115F9-EB85X-CD6
µ
PD29F064115F9-EB90X-CD6
µ
PD29F064115F9-EB85X-CD5
µ
PD29F064115F9-EB90X-CD5
80
85
80
85
80
85
85
90
85
90
85
90
1.95
±
0.15
85-pin TAPE FBGA (11
×
8)
1.8
±
0.15
48-pin PLASTIC TSOP (I) (12
×
20)
(Normal bent)
63-pin TAPE FBGA (11
×
8)
85-pin TAPE FBGA (11
×
8)
2
Data Sheet M16062EJ2V0DS
µ
PD29F064115-X
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12
×
20) (Normal bent)
[
µ
PD29F064115GZ-DB80X-MJH ]
[
µ
PD29F064115GZ-DB85X-MJH ]
[
µ
PD29F064115GZ-EB85X-MJH ]
[
µ
PD29F064115GZ-EB90X-MJH ]
Marking Side
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
/WE
/RESET
A21
/WP (ACC)
RY (/BY)
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
CC
Q
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
V
CC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
/OE
GND
/CE
A0
A0 to A21
/CE
/WE
/OE
/RESET
RY (/BY)
/WP (ACC)
V
CC
V
CC
Q
GND
: Address inputs
: Chip Enable
: Write Enable
: Output Enable
: Hardware reset input
: Ready (Busy) output
: Write Protect (Accelerated) input
: Supply Voltage
: Input / Output Supply Voltage
: Ground
I/O0 to I/O15 : Data Inputs / Outputs
Remark
Refer to
Package Drawings
for the 1-pin index mark.
Data Sheet M16062EJ2V0DS
3
µ
PD29F064115-X
85-pin TAPE FBGA (11
×
8)
[
µ
PD29F064115F9-DB80X-CD5 ]
[
µ
PD29F064115F9-DB85X-CD5 ]
[
µ
PD29F064115F9-EB85X-CD5 ]
[
µ
PD29F064115F9-EB90X-CD5 ]
Top View
Top View
10
9
8
7
6
5
4
3
2
1
Bottom View
Bottom View
A B C D E F G H J K L M
A B C D E F G H
A
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
B
NC
NC
8
NC
7
6
NC
5
NC
4
3
NC
2
NC
1
NC
B
C
A15
A21
A15
NC
A12
A11
A13
A11
A13
A12
A19
A9
A8
A8
A19
A9
/WE
NC
A20
CE2s
A20
/WE
/WP(ACC) /RESET RY(/BY)
/WP(ACC) /RESET RY(/BY)
A18
NC
NC
A18
/LB
/UB
A6
A7
A5
A7
A6
A5
A2
A3
A3
A2
NC
A
C
D
E
M L K J H G F E D C B A
Top View
F
NC
D
NC
NC
A14
A14
A10
A10
G
NC
E
A16
A16
NC
SA
I/O6
I/O6
H G F E D C B A
H
J
K
L
NC
G
H
F
NC
GND
CIOf
V
SS
I/O15
I/O14
I/O7
I/O15, A-1 I/O7
I/O14
I/O13
I/O12
I/O5
I/O12
I/O5
I/O13
V
CC
Q
I/O4
NC
I/O4
CIOs
V
CC
s
I/O3
I/O11
V
CC
V
CC
f
I/O3
I/O11
I/O2
I/O9
I/O10
I/O9
I/O10
I/O2
I/O0
/OE
I/O8
/OE
I/O0
I/O8
NC
/CE
/CEf
/CE1s
NC
NC
M
NC
NC
Top View
NC
NC
A17
A17
A4
A4
A1
A1
NC
I/O1
I/O1
GND
V
SS
A0
A0
NC
NC
NC
NC
NC
NC
A0 to A21
/CE
/WE
/OE
/RESET
RY (/BY)
/WP (ACC)
V
CC
V
CC
Q
GND
NC
Note
: Address inputs
: Chip Enable
: Write Enable
: Output Enable
: Hardware reset input
: Ready (Busy) output
: Write Protect (Accelerated) input
: Supply Voltage
: Input / Output Supply Voltage
: Ground
: No Connection
I/O0 to I/O15 : Data Inputs / Outputs
Note
Some signals can be applied because this pin is not connected to the inside of the chip.
Remark
Refer to
Package Drawings
for the index mark.
INPUT / OUTPUT PIN FUNCTION
Refer to
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Data Sheet M16062EJ2V0DS
5
PCB Design
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