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K3N3C1000D-GC12

Description
MASK ROM, 256KX16, 120ns, CMOS, PDSO40, 0.525 INCH, SOP-40
Categorystorage    storage   
File Size48KB,3 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K3N3C1000D-GC12 Overview

MASK ROM, 256KX16, 120ns, CMOS, PDSO40, 0.525 INCH, SOP-40

K3N3C1000D-GC12 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
Parts packaging codeSOIC
package instructionSOP, SOP40,.56
Contacts40
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time120 ns
Other featuresALL INPUTS AND OUTPUTS TTL COMPATIBLE
Spare memory width8
JESD-30 codeR-PDSO-G40
JESD-609 codee0
length25.65 mm
memory density4194304 bit
Memory IC TypeMASK ROM
memory width16
Number of functions1
Number of terminals40
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX16
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP40,.56
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height2.8 mm
Maximum standby current0.00005 A
Maximum slew rate0.05 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.67 mm
K3N3C1000D-D(G)C
4M-Bit (512Kx8 /256Kx16) CMOS MASK ROM
FEATURES
Switchable orginization
524,288 x 8(byte mode)
262,144 x 16(word mode)
Fast access time : 80ns(Max.)
Supply voltage : single +5V
Current consumption
Operating : 50mA(Max.)
Standby : 50µA(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
-. K3N3C1000D-DC : 40-DIP-600
-. K3N3C1000D-GC : 40-SOP-525
CMOS MASK ROM
GENERAL DESCRIPTION
The K3N3C1000D-D(G)C is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 524,288 x 8 bit(byte mode) or as
262,144 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N3C1000D-DC is packaged in a 40-DIP and the
K3N3C1000D-GC in a 40-SOP.
FUNCTIONAL BLOCK DIAGRAM
A
17
PIN CONFIGURATION
.
.
.
.
.
.
.
.
A
0
A
-1
X
BUFFERS
AND
DECORDER
MEMORY CELL
MATRIX
(262,144x16/
524,288x8)
A
17
1
2
3
4
5
6
7
8
9
40
39
A
8
A
9
Y
BUFFERS
AND
DECORDER
SENSE AMP.
DATA OUT
BUFFERS
A
7
A
6
A
5
A
4
A
3
A
2
38 A
10
37
36
A
11
A
12
35 A
13
34
A
14
. . .
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
A
1
A
0
CE 10
V
SS
11
DIP
&
SOP
33 A
15
32 A
16
31 BHE
30 V
SS
29 Q
15
/A
-1
28 Q
7
27 Q
14
26 Q
6
25 Q
13
24 Q
5
23 Q
12
22 Q
4
21 V
CC
OE 12
Q
0
13
Q
8
14
Q
1
Q
9
15
16
17
18
19
Pin Name
A
0
- A
17
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
Pin Function
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power(+5.0V)
Ground
Q
2
Q
10
Q
3
Q
11
20
K3N3C1000D-D(G)C
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