DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD23C32340, 23C32380
32M-BIT MASK-PROGRAMMABLE ROM
4M-WORD BY 8-BIT (BYTE MODE) / 2M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The
µ
PD23C32340 and
µ
PD23C32380 are 33,554,432 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 4,194,304 words by 8 bits, WORD mode : 2,097,152 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
µ
PD23C32340 and
µ
PD23C32380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA.
Features
•
Pin compatible with NOR Flash Memory
•
Word organization
4,194,304 words by 8 bits (BYTE mode)
2,097,152 words by 16 bits (WORD mode)
•
Page access mode
BYTE mode : 8 byte random page access (
µ
PD23C32340)
16 byte random page access (
µ
PD23C32380)
WORD mode : 4 word random page access (
µ
PD23C32340)
8 word random page access (
µ
PD23C32380)
•
Operating supply voltage : V
CC
= 2.7 V to 3.6 V
Operating supply
voltage
V
CC
3.0 V
±
0.3 V
3.3 V
±
0.3 V
Access time /
Page access time
ns (MAX.)
100 / 25
90 / 25
Power supply current (Active mode)
mA (MAX.)
Standby current
(CMOS level input)
µ
PD23C32340
40
µ
PD23C32380
55
µ
A (MAX.)
30
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15711EJ2V0DS00 (2nd edition)
Date Published February 2003 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
µ
PD23C32340, 23C32380
Ordering Information
Part Number
Package
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
48-pin TAPE FBGA (8 x 6)
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
48-pin TAPE FBGA (8 x 6)
µ
PD23C32340GZ-xxx-MJH
µ
PD23C32340F9-xxx-BC3
µ
PD23C32380GZ-xxx-MJH
µ
PD23C32380F9-xxx-BC3
(xxx : ROM code suffix No.)
2
Data Sheet M15711EJ2V0DS
µ
PD23C32340, 23C32380
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
[
µ
PD23C32340GZ-xxx-MJH ]
[
µ
PD23C32380GZ-xxx-MJH ]
Marking Side
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
WORD, /BYTE
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
/CE
A0
A0 to A20
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
/CE
/OE or OE
V
CC
GND
NC
DC
Note
: Mode select
: Chip Enable
: Output Enable
: Supply voltage
: Ground
: No Connection
: Don’t Care
Note
Some signals can be applied because this pin is not connected to the inside of the chip.
Remark
Refer to
Package Drawings
for the 1-pin index mark.
Data Sheet M15711EJ2V0DS
3
µ
PD23C32340, 23C32380
48-pin TAPE FBGA (8 x 6)
[
µ
PD23C32340F9-xxx-BC3 ]
[
µ
PD23C32380F9-xxx-BC3 ]
Top View
Bottom View
6
5
4
3
2
1
A
B
C
D
E
F
G
H
H
G
F
E
D
C
B
A
A
6
A13
B
A12
C
A14
D
A15
E
A16
F
WORD,
/BYTE
G
O15,
A–1
O13
V
CC
O11
O9
/OE or
OE
H
GND
6
H
GND
G
O15,
A–1
F
WORD,
/BYTE
O14
O12
O10
O8
/CE
E
A16
D
A15
C
A14
B
A12
A
A13
5
4
3
2
1
A9
NC
NC
A7
A3
A8
NC
NC
A17
A4
A10
NC
A18
A6
A2
A11
A19
A20
A5
A1
O7
O5
O2
O0
A0
O14
O12
O10
O8
/CE
O6
O4
O3
O1
GND
5
4
3
2
1
O6
O4
O3
O1
GND
O13
V
CC
O11
O9
/OE or
OE
O7
O5
O2
O0
A0
A11
A19
A20
A5
A1
A10
NC
A18
A6
A2
A8
NC
NC
A17
A4
A9
NC
NC
A7
A3
A0 to A20
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
/CE
/OE or OE
V
CC
GND
NC
DC
Note
: Mode select
: Chip Enable
: Output Enable
: Supply voltage
: Ground
: No Connection
: Don’t Care
Note
Some signals can be applied because this pin is not connected to the inside of the chip.
Remark
Refer to
Package Drawings
for the index mark.
4
Data Sheet M15711EJ2V0DS
µ
PD23C32340, 23C32380
Input / Output Pin Functions
Pin name
WORD, /BYTE
Input / Output
Input
Function
The pin for switching WORD mode and BYTE mode.
High level
: WORD mode (2M-word by 16-bit)
Low level
: BYTE mode (4M-word by 8-bit)
A0 to A20
(Address inputs)
Input
Address input pins.
A0 to A20 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
A0 to A20 are used as 21 bits address signals.
BYTE mode (4M-word by 8-bit)
A0 to A20 are used as the upper 21 bits of total 22 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
O0 to O7, O8 to O14
(Data outputs)
Output
Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (4M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
(Data output 15,
LSB Address input)
Output, Input
O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (2M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (4M-word by 8-bit)
The least significant address bus (A−1).
/CE
(Chip Enable)
Input
Chip activating signal.
When the OE is active, output states are following.
High level
: High-Z
Low level
: Data out
/OE or OE or DC
(Output Enable, Don't care)
V
CC
GND
NC
−
−
−
Input
Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
Supply voltage
Ground
Not internally connected. (The signal can be connected.)
Data Sheet M15711EJ2V0DS
5
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