Mobile Intel
Pentium
4
Processor-M
Datasheet
June 2002
Order Number: 250686-003
Mobile Intel
Pentium
4 Processor-M
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infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale
for such products. Information contained herein supersedes previously published specifications on these devices from Intel.
Actual system-level properties, such as skin temperature, are a function of various factors, including component placement,
component power characteristics, system power and thermal management techniques, software application usage and general
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deviate from published specifications. Current characterized errata are available on request.
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* Other brands and names are the property of their respective owners.
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Datasheet
250686-003
Mobile Intel
Pentium
4 Processor-M
Contents
1.
Introduction......................................................................................................................... 9
1.1
1.2
2.
2.1
2.2
2.3
Terminology.........................................................................................................10
1.1.1 Terminology............................................................................................10
References ..........................................................................................................11
System Bus and GTLREF ...................................................................................12
Power and Ground Pins ......................................................................................12
Decoupling Guidelines ........................................................................................12
2.3.1 VCC Decoupling .....................................................................................13
2.3.2 System Bus AGTL+ Decoupling.............................................................13
2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking .......................13
Voltage Identification and Power Sequencing.....................................................13
2.4.1 Enhanced Intel
SpeedStep
Technology.............................................15
2.4.2 Phase Lock Loop (PLL) Power and Filter...............................................15
2.4.3 Catastrophic Thermal Protection............................................................17
Signal Terminations, Unused Pins and TESTHI[10:0] ........................................17
System Bus Signal Groups .................................................................................19
Asynchronous GTL+ Signals...............................................................................21
Test Access Port (TAP) Connection....................................................................21
System Bus Frequency Select Signals (BSEL[1:0])............................................21
Maximum Ratings................................................................................................22
Processor DC Specifications...............................................................................22
AGTL+ System Bus Specifications .....................................................................33
System Bus AC Specifications ............................................................................34
Processor AC Timing Waveforms .......................................................................39
System Bus Clock (BCLK) Signal Quality Specifications and Measurement
Guidelines ...........................................................................................................50
System Bus Signal Quality Specifications and Measurement Guidelines...........51
System Bus Signal Quality Specifications and Measurement Guidelines...........54
3.3.1 Overshoot/Undershoot Guidelines .........................................................54
3.3.2 Overshoot/Undershoot Magnitude .........................................................54
3.3.3 Overshoot/Undershoot Pulse Duration...................................................54
3.3.4 Activity Factor .........................................................................................55
3.3.5 Reading Overshoot/Undershoot Specification Tables............................55
3.3.6 Conformance Determination to Overshoot/Undershoot Specifications ..56
Processor Pin-Out ...............................................................................................62
Mobile Intel Pentium 4 Processor-M Pin Assignments........................................64
Alphabetical Signals Reference ..........................................................................78
Electrical Specifications....................................................................................................12
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
3.2
3.3
System Bus Signal Quality Specifications........................................................................50
4.
5.
Package Mechanical Specifications .................................................................................59
4.1
5.1
5.2
Pin Listing and Signal Definitions .....................................................................................64
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Mobile Intel
Pentium
4 Processor-M
6.
Thermal Specifications and Design Considerations......................................................... 86
6.1
Thermal Specifications........................................................................................ 87
6.1.1 Thermal Diode........................................................................................ 87
6.1.2 Thermal Monitor ..................................................................................... 88
Power-On Configuration Options ........................................................................ 90
Clock Control and Low Power States.................................................................. 90
7.2.1 Normal State .......................................................................................... 90
7.2.2 AutoHALT Powerdown State ................................................................. 90
7.2.3 Stop-Grant State .................................................................................... 91
7.2.4 HALT/Grant Snoop State ....................................................................... 92
7.2.5 Sleep State............................................................................................. 92
7.2.6 Deep Sleep State ................................................................................... 92
7.2.7 Deeper Sleep State................................................................................ 93
Enhanced Intel SpeedStep Technology.............................................................. 93
Logic Analyzer Interface (LAI)............................................................................ 94
8.1.1 Mechanical Considerations .................................................................... 94
8.1.2 Electrical Considerations........................................................................ 94
7.
Configuration and Low Power Features........................................................................... 90
7.1
7.2
7.3
8.
8.1
Debug Tools Specifications.............................................................................................. 94
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Datasheet
250686-003
Mobile Intel
Pentium
4 Processor-M
Figures
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VCCVID Pin Voltage and Current Requirements ................................................14
Typical VCCIOPLL, VCCA, VSSA Power Distribution ........................................16
Phase Lock Loop (PLL) Filter Requirements ......................................................17
Illustration of VCC Static and Transient Tolerances (VID = 1.30 V)....................25
Illustration of VCC Static and Transient Tolerances (VID = 1.20 V)....................27
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID Setting =
1.30 V).................................................................................................................28
ITPCLKOUT[1:0] Output Buffer Diagram ............................................................33
AC Test Circuit ....................................................................................................40
TCK Clock Waveform..........................................................................................40
Differential Clock Waveform................................................................................41
Differential Clock Crosspoint Specification..........................................................42
System Bus Common Clock Valid Delay Timings...............................................42
System Bus Reset and Configuration Timings....................................................43
Source Synchronous 2X (Address) Timings .......................................................43
Source Synchronous 4X Timings ........................................................................44
Power Up Sequence ...........................................................................................45
Power Down Sequence.......................................................................................45
Test Reset Timings .............................................................................................46
THERMTRIP# to Vcc Timing...............................................................................46
FERR#/PBE# Valid Delay Timing .......................................................................46
TAP Valid Delay Timing ......................................................................................47
ITPCLKOUT Valid Delay Timing .........................................................................47
Stop Grant/Sleep/Deep Sleep Timing .................................................................48
Enhanced Intel SpeedStep Technology/Deep Sleep Timing ..............................49
BCLK Signal Integrity Waveform.........................................................................51
Low-to-High System Bus Receiver Ringback Tolerance.....................................52
High-to-Low System Bus Receiver Ringback Tolerance.....................................52
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers .........................................................................................................53
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and
TAP Buffers .........................................................................................................53
Maximum Acceptable Overshoot/Undershoot Waveform ...................................58
Micro-FCPGA Package Top and Bottom Isometric Views ..................................59
Micro-FCPGA Package - Top and Side Views....................................................60
Micro-FCPGA Package - Bottom View................................................................62
The Coordinates of the Processor Pins as Viewed From the Top of the
Package. .............................................................................................................63
Clock Control States............................................................................................91
250686-003
Datasheet
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