DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD178F098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD178F098 is a flash memory model of the
µ
PD178076, 178078, 178096, and 178098, and is provided with
a flash memory to/from which data can be written/erased with the microcontroller mounted on a printed circuit board.
For the detailed functional description, refer to the following User’s Manuals:
µ
PD178078, 178098 Subseries User’s Manual: U12790E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
• Serial interface (UART mode)
• IEBus
TM
controller
• Pin-compatible with mask ROM models (except V
PP
pin)
• Flash memory: 60K bytes
Note
• Internal high-speed RAM: 1024 bytes
• Internal extension RAM: 2048 bytes
Note
• Buffer RAM: 32 bytes
• Operable at same supply voltage as mask ROM models (V
DD
= 4.5 to 5.5 V during PLL operation)
Note
The capacities of the flash memory and internal extension RAM can be changed using the memory size
select register (IMS) and internal extension RAM size select register (IXS).
Remark
For the differences between the flash memory model and mask ROM models, refer to
1. DIFFERENCES
BETWEEN
µ
PD178F098 AND MASK ROM MODELS.
The electrical specifications (such as supply current) in the
µ
PD178F098 differ from those of the
mask ROM models. Confirm these differences before mass-producing any application set.
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
Package
100-pin plastic QFP (14
×
20)
µ
PD178F098GF-3BA
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12920EJ1V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µ
PD178F098
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production
Models under development
Flash memory model or
PROM model
Mask ROM model
80 pins
µ
PD178F048
Internal OSD controller
8-bit PWM
×
4 channels
14-bit PWM
×
1 channel
80 pins
µ
PD178048 subseries
Internal OSD controller
8-bit PWM
×
4 channels
14-bit PWM
×
1 channel
100 pins
µ
PD178098 subseries
Internal IEBus controller
100 pins
µ
PD178F098
Internal IEBus controller and UART
100 pins
µ
PD178078 subseries
Internal UART
80 pins
µ
PD178F134
Internal LCD and UART
80 pins
µ
PD178034 subseries
Internal LCD and UART
80 pins
µ
PD178F124
Internal UART
80 pins
µ
PD178024 subseries
Internal UART
80 pins
µ
PD178018A subseries
80 pins
µ
PD178P018A
80 pins
µ
PD178003 subseries
Limits functions of
µ
PD178018A subseries
2
Data Sheet U12920EJ1V0DS00
µ
PD178F098
FUNCTIONAL OUTLINE
(1/2)
Item
Internal
memory
Flash memory
60K bytes
Functions
High-speed RAM 1024 bytes
Buffer RAM
Extension RAM
32 bytes
2048 bytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
• 0.32
µ
s/0.64
µ
s/1.27
µ
s/2.54
µ
s/5.08
µ
s (with crystal resonator of f
X
= 6.3 MHz)
• 0.44
µ
s/0.89
µ
s/1.78
µ
s/3.56
µ
s/7.11
µ
s (with crystal resonator of f
X
= 4.5 MHz)
Note 1
•
•
•
•
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test Boolean operation)
BCD adjustment, etc.
: 80 pins
:
8 pins
: 64 pins
8 pins
General-purpose register
Minimum instruction execution
time
Instruction set
I/O port
Total
• CMOS input
• CMOS I/O
• N-ch open-drain output :
A/D converter
Serial interface
8-bit resolution
×
8 channels
• 3-wire/SBI/2-wire/I
2
C bus
Note 2
mode selectable
: 1 channel
• 3-wire mode
: 1 channel
• 3-wire mode (with automatic transmit/receive function of up to 32 bytes): 1 channel
• UART mode
: 1 channel
Provided
•
•
•
•
Basic timer (timer carry FF (10 Hz))
16-bit timer/event counter
8-bit timer/event counter
Watchdog timer
:
:
:
:
1
1
2
1
channel
channel
channels
channel
IEBus controller
Timer
Buzzer output
BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz
BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of f
X
= 6.3 MHz)
Vectored
interrupt
source
PLL
frequency
synthesizer
Maskable
Non-maskable
Software
Division mode
Internal : 15, External: 8
Internal: 1
1
2 types
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOL and VCOH pins)
Reference
frequency
Charge pump
Phase
comparator
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Error out output: 2 pins
Unlock detectable in software
Notes 1.
When using the IEBus controller, the 4.5-MHz crystal resonator cannot be used. Use the 6.3-MHz
crystal resonator.
2.
When the I
2
C bus mode is used (including when the mode is implemented in software without using
the peripheral hardware), consult NEC when ordering a mask.
Data Sheet U12920EJ1V0DS00
3
µ
PD178F098
(2/2)
Item
Frequency counter
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
Standby function
Reset
• HALT mode
• STOP mode
•
•
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Reset by power-ON clear circuit
Detection of less than 4.5 V
Note
(Reset does not occur, however.)
Detection of less than 3.5 V
Note
(during CPU operation)
Detection of less than 2.3 V
Note
(in STOP mode)
Functions
Supply voltage
Package
• V
DD
= 4.5 to 5.5 V (during CPU, PLL operation)
• V
DD
= 3.5 to 5.5 V (during CPU operation)
100-pin plastic QFP (14
×
20)
Note
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
4
Data Sheet U12920EJ1V0DS00
µ
PD178F098
PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (14
×
20)
µ
PD178F098GF-3BA
GNDPORT
V
DD
PORT
P47
P46
P45
P44
P43
P42
P41
P40
P67
P66
P65
P64
P63
P62
P61
P60
GND1
P07/INTP7
P00/INTP0
P01/INTP1
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI3
P71/SO3
P72/SCK3
P73
P50
P51
P52
P53
P54
P55
P56
P57
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
AV
DD
P14/ANI4
P15/ANI5
P16/ANI6
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P06/INTP6
P05/INTP5
P04/INTP4
P124
P123
P122
P121/RX0
P120/TX0
P77
P76
P75/TXD0
P74/RXD0
P137
P136
P135
P134
P133
P132
P131/TO51
P130/TO50
P37/BUZ
P36/BEEP0
P35/TI51
P34/TI50
P33/TI01
P32/TI00
P31/TO0
P30/VM45
P03/INTP3
P02/INTP2
Cautions 1. Directly connect the V
PP
pin to GND0, GND1, or GND2 in normal operating mode.
2. Keep the voltage at AV
DD
, V
DD
PORT, and V
DD
PLL same as that at the V
DD
pin.
3. Keep the voltage at AV
SS
, GNDPORT, and GNDPLL same as that at GND0, GND1, or GND2.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-
µ
F capacitor.
P17/ANI7
AV
SS
REGCPU
V
DD
REGOSC
X2
X1
GND0
P100
GND2
P101/AMIFC
P102/FMIFC
V
DD
PLL
VCOH
VCOL
GNDPLL
EO0
EO1
V
PP
RESET
Data Sheet U12920EJ1V0DS00
5