DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD178076,178078,178096,178098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD178076, 178078, 178096, and 178098 are 8-bit single-chip CMOS microcontrollers containing hardware
for digital tuning systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In
addition, the
µ
PD178076 and 178078 have an asynchronous serial interface (UART) mode, and the
µ
PD178096 and
178098 have an IEBus
TM
controller.
Moreover, a flash memory model, the
µ
PD178F098, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µ
PD178078, 178098 Subseries User’s Manual : U12790E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
•
High-capacity ROM and RAM
Item Program Memory (ROM)
Part Number
Data Memory
Internal high-speed RAM Internal buffer RAM
48K bytes
60K bytes
1024 bytes
32 bytes
Internal extension RAM
1024 bytes
2048 bytes
µ
PD178076, 178096
•
Instruction cycle:
µ
PD178078, 178098
0.32
µ
s (with crystal resonator of f
X
= 6.3 MHz)
•
Hardware for PLL frequency synthesizer
phase comparator, charge pump
dual modulus prescaler, programmable divider,
•
Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (UART mode:
µ
PD178076 and 178078
•
Vectored interrupt sources
•
Supply voltage
•
µ
PD178076, 178078: 22
•
µ
PD178096, 178098: 21
only), IEBus controller (
µ
PD178096 and 178098
only), timers, frequency counter, power-ON clear
circuit
:V
DD
= 4.5 to 5.5 V (during PLL and CPU
operations)
:V
DD
= 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12885EJ3V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 2000
µ
PD178076, 178078, 178096, 178098
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
Package
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
100-pin plastic QFP (14
×
20)
µ
PD178076GF-×××-3BA
µ
PD178078GF-×××-3BA
µ
PD178096GF-×××-3BA
µ
PD178098GF-×××-3BA
Remark
×××
indicates ROM code suffix, which is E×× when the I
2
C bus is used.
2
Data Sheet U12885EJ3V0DS00
µ
PD178076, 178078, 178096, 178098
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production
Models under development
Flash memory model or
PROM model
Mask ROM model
80 pins
µ
PD178F048
Internal OSD controller
8-bit PWM
×
4 channels
14-bit PWM
×
1 channel
80 pins
µ
PD178048 subseries
Internal OSD controller
8-bit PWM
×
4 channels
14-bit PWM
×
1 channel
100 pins
µ
PD178098 subseries
Internal IEBus controller
100 pins
µ
PD178F098
Internal IEBus controller and UART
100 pins
µ
PD178078 subseries
Internal UART
80 pins
µ
PD178F134
Internal LCD and UART
80 pins
µ
PD178034 subseries
Internal LCD and UART
80 pins
µ
PD178F124
Internal UART
80 pins
µ
PD178024 subseries
Internal UART
80 pins
µ
PD178018A subseries
80 pins
µ
PD178P018A
80 pins
µ
PD178003 subseries
Limits functions of
µ
PD178018A subseries
Data Sheet U12885EJ3V0DS00
3
µ
PD178076, 178078, 178096, 178098
FUNCTIONAL OUTLINE
(1/2)
Item
Internal
memory
ROM
µ
PD178076
48K bytes
µ
PD178078
60K bytes
µ
PD178096
48K bytes
µ
PD178098
60K bytes
High-speed RAM 1024 bytes
Buffer RAM
Extension RAM
32 bytes
1024 bytes
2048 bytes
1024 bytes
2048 bytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
• 0.32
µ
s/0.64
µ
s/1.27
µ
s/2.54
µ
s/5.08
µ
s (with crystal resonator of f
X
= 6.3 MHz)
• 0.44
µ
s/0.89
µ
s/1.78
µ
s/3.56
µ
s/7.11
µ
s (with crystal resonator of f
X
= 4.5 MHz)
Note 1
•
•
•
•
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test Boolean operation)
BCD adjustment, etc.
: 80 pins
:
8 pins
: 64 pins
8 pins
• 3-wire/SBI/2-wire/I
2
C bus
Note 2
mode
selectable: 1 channel
• 3-wire mode: 1 channel
• 3-wire mode (with automatic transmit/
receive function of up to 32 bytes):
1 channel
Provided
: 1 channel
: 1 channel
: 2 channels
: 1 channel
General-purpose register
Minimum instruction execution
time
Instruction set
I/O port
Total
• CMOS input
• CMOS I/O
• N-ch open-drain output :
A/D converter
Serial interface
8-bit resolution
×
8 channels
• 3-wire/SBI/2-wire/I
2
C bus
Note 2
mode
selectable: 1 channel
• 3-wire mode: 1 channel
• 3-wire mode (with automatic transmit/
receive function of up to 32 bytes):
1 channel
• UART mode: 1 channel
IEBus controller
Timer
Not provided
• Basic timer (timer carry FF (10 Hz))
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watchdog timer
Buzzer output
BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz
BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of f
X
= 6.3 MHz)
Notes 1.
When using the IEBus controller of the
µ
PD178096 or 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
2.
When the I
2
C bus mode is used (including when the mode is implemented in software without using
the peripheral hardware), consult NEC when ordering a mask.
4
Data Sheet U12885EJ3V0DS00
µ
PD178076, 178078, 178096, 178098
(2/2)
Item
Vectored
interrupt
source
Non-maskable
Software
PLL
frequency
synthesizer
Reference
frequency
Charge pump
Phase
comparator
Frequency counter
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
• HALT mode
• STOP mode
Reset
• Reset by RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit
• Detection of less than 4.5 V
Note
(Reset does not occur, however.)
• Detection of less than 3.5 V
Note
(during CPU operation)
• Detection of less than 2.3 V
Note
(in STOP mode)
Supply voltage
Package
• V
DD
= 4.5 to 5.5 V (during CPU, PLL operation)
• V
DD
= 3.5 to 5.5 V (during CPU operation)
• 100-pin plastic QFP (14
×
20)
Division mode
Maskable
µ
PD178076
Internal : 13
External: 8
Internal: 1
1
2 types
µ
PD178078
µ
PD178096
Internal : 12
External: 8
µ
PD178098
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOL and VCOH pins)
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Error out output: 2 pins
Unlock detectable in software
Standby function
Note
These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U12885EJ3V0DS00
5
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