HV506
Preliminary
275V 40-Channel Row Driver with SCR Outputs
Ordering Information
Package Options
Device
80-Lead
Ceramic Gullwing
HV506DG
64-Lead 3-Sided
Plastic Gullwing
HV506PG
Die
HV506X
HV506
Features
❏
Processed with HVDI
technology
❏
Symmetric row drive
❏
Output voltage up to 275V
❏
Source/Sink current 300mA (min.)
❏
Shift Register Speed 3MHz
❏
Pin-programmable shift direction (DIR)
❏
Hi-Rel processing available
General Description
The HV506 is a low-voltage serial to high-voltage parallel con-
verter with push-pull outputs. It is especially suitable for use as
a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
When the data reset pin (DR
IO
) is at logic high, it will reset all the
outputs of the internal shift register to zero. At the same time, the
output of the shift register will start shifting a logic high from the
least significant bit to the most significant bit. The DR
IO
can be
triggered at any time. The DIR pin controls the direction of data
through the device. When DIR is at logic high, DR
IOA
is the input
and DR
IOB
is the output. When DIR is grounded, DR
IOB
is the input
and the DR
IOA
is the output. See the Output Sequence Operation
Table for output sequence. The POL and OE pins perform the
polarity select and output enable function respectively. Data is
clocked through the shift register loaded on the low to high
transition of the clock. A logic high in the shift register will cause
the other corresponding output to swing to V
DD
if POL is high, or
to V
SS
if POL is low. All other outputs will be in the High-Z state.
If OE is at logic high all outputs will be in the High-Z state. An
output in the High-Z state may block up to 275V above V
SS
or
275V below V
DD
. The D
P
/D
N
pins are for the positive/negative
discharge of the high voltage output HV
OUT
. Data output buffers
are provided for cascading devices.
LV
DD
requires low current for the HV506 logic section. V
DD
requires high current for the output section . Typically these two
pins are at the same potential. The same current and potential
conditions apply to the LV
SS
, logic, and V
SS
, output pins. V
sub
must
always be equal or greater than the most positive supply.
Absolute Maximum Ratings
Logic supply voltage, LV
DD1
Output supply voltage, V
DD1
Substrate bias voltage, V
sub
Output voltage, HV
OUT
Logic input levels
Continuous total power dissipation
2
Ceramic
Plastic
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes:
1. All voltages are referenced to V
SS
.
2. For operation above 25°C ambient derate linearly to maximum operating
temperture at 20mW/°C for plasitc and at 19mW/°C for ceramic.
3. V
sub
must be the most positive with respect to V
SS
.
-0.5V to +15V
-0.5V to +15V
See Note 3
±300V
-0.5V to V
DD
+0.5V
1900mW
1200mW
Plastic
-40°C to +85°C
Ceramic -55°C to +125°C
-65°C to +150°C
260°C
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
1
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
HV506
AC Characteristics
Symbol
f
CLK
t
W (H/L)
t
SUD
t
HD
t
SUC
t
SUE
t
HC
t
HE
t
DHL*
t
DLH*
t
OFF(SCR)
t
OFF(D)
t
POW
t
OEW
SR
Parameter
Clock frequency
Pulse width - clock high or low
Data set-up time before clock rises
Data hold time after clock rises
HV
OUT
delay from clock rises (Hi-Z to H or L)
HV
OUT
delay from Output Enable rises
HV
OUT
delay from clock rises (H or L to Hi-Z)
HV
OUT
delay from Output Enable rises
Delay time clock to data output falls
Delay time clock to data output rises
Turn off time of output SCR
Turn off time of output diode
POL pulse width
Output Enable pulse width
Slew rate of HV
OUT
3
3
200
150
50
50
1
600
2
600
250
250
4
2
Min
Max
3
Units
MHz
ns
ns
ns
µs
ns
µs
ns
ns
ns
µs
µs
µs
µs
V/µs
C
L
= 10nF
C
L
= 10nF
C
L
= 10nF
C
L
= 10nF
C
L
= 15pF
C
L
= 15pF
Time after I
OUT
≤
2mA,
C
L
= 10nF
Time after I
OUT
≤
2mA,
C
L
= 10nF
Conditions
* The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is
equal to t
WH
. Therefore the delay is measured from the trailing edge of the clock.
3
Talking
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