WEDPN8M64V-125BI datasheet, PDF

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WEDPN8M64V-125BI: DescriptionSynchronous DRAM Module, 8MX64, 6ns, CMOS, PBGA219, PLASTIC, BGA-219; Categorystorage storage; File Size359KB，12 Pages; ManufacturerWhite Microelectronics

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WEDPN8M64V-125BI Overview

Synchronous DRAM Module, 8MX64, 6ns, CMOS, PBGA219, PLASTIC, BGA-219

WEDPN8M64V-125BI Parametric

Parameter Name	Attribute value
Maker	White Microelectronics
package instruction	,
Reach Compliance Code	unknown
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	S-PBGA-B219
memory density	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	219
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX64
Package body material	PLASTIC/EPOXY
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal location	BOTTOM

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WEDPN8M64V-XBX

HI-RELIABILITY PRODUCT

8Mx64 Synchronous DRAM

FEATURES

High Frequency = 100, 125MHz

Package:

• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm

Single 3.3V

±0.3V

power supply

Unbuffered

ADVANCED*

GENERAL DESCRIPTION

The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic

random-access ,memory using 4 chips containing 134,217,728

bits. Each chip is internally configured as a quad-bank DRAM with

a synchronous interface. Each of the chip’s 33,554,432-bit banks

is organized as 4,096 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a pro-

grammed number of locations in a programmed sequence. Ac-

cesses begin with the registration of an ACTIVE command, which

is then followed by a READ or WRITE command. The address bits

registered coincident with the ACTIVE command are used to

select the bank and row to be accessed (BA

, BA

select the bank;

0-11

select the row). The address bits registered coincident with

the READ or WRITE command are used to select the starting

column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths

of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option.

An AUTO PRECHARGE function may be enabled to provide a self-

timed row precharge that is initiated at the end of the burst sequence.

The 512Mb SDRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compatible with the 2n rule

of prefetch architectures, but it also allows the column address to be

changed on every clock cycle to achieve a high-speed, fully random

access. Precharging one bank while accessing one of the other three

banks will hide the precharge cycles and provide seamless, high-

speed, random-access operation.

The 512Mb SDRAM is designed to operate in 3.3V, low-power

memory systems. An auto refresh mode is provided, along with a

power-saving, power-down mode.

All inputs and outputs are LVTTL compatible. SDRAMs offer substan-

tial advances in DRAM operating performance, including the ability to

synchronously burst data at a high data rate with automatic column-

address generation, the ability to interleave between internal banks

in order to hide precharge time and the capability to randomly change

column addresses on each clock cycle during a burst access.

Fully Synchronous; all signals registered on positive edge of

system clock cycle

Internal pipelined operation; column address can be changed

every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

4096 refresh cycles

Commercial, Industrial and Military Temperature Ranges

Organized as 8M x 64

Weight: WEDPN8M64V-XBX - 2.5 grams typical

BENEFITS

41% SPACE SAVINGS

Reduced part count

Low Profile: 2:20 mm (0.87) Max

Reduced trace lengths for lower parasitic capacitance

BT laminate interposer for optimum TCE match

Suitable for hi-reliability applications

Upgradeable to 16M x 64 density (contact factory for information)

* This data sheet describes a product under development, not fully

characterized, and is subject to change without notice.

Discrete Approach

11.9

ACTUAL SIZE

22.3

41%

Area

June 2000 Rev. 5

4 x 265mm

= 1061mm

625mm

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

WEDPN8M64V-125BI Related Products

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Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	6 ns	6 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	S-PBGA-B219	S-PBGA-B219	S-PBGA-B219	S-PBGA-B219	S-PBGA-B219	S-PBGA-B219
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
memory width	64	64	64	64	64	64
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	219	219	219	219	219	219
word count	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	70 °C	125 °C	85 °C	70 °C	125 °C
Minimum operating temperature	-40 °C	-	-55 °C	-40 °C	-	-55 °C
organize	8MX64	8MX64	8MX64	8MX64	8MX64	8MX64
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
self refresh	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	MILITARY	INDUSTRIAL	COMMERCIAL	MILITARY
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maker	White Microelectronics	-	-	White Microelectronics	White Microelectronics	White Microelectronics

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