DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD160010
384-/360-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256 GRAY SCALES, mini-LVDS INTERFACE SUPPORTED)
DESCRIPTION
The
µ
PD160010 is a source driver for TFT-LCDS that supports the display of 256 gray scales and employs mini-LVDS
interface. Which can realize a full-color display of 16,777,216 colors by output of 256 values
γ
-corrected by an internal D/A
converter and 10-by-2 external power modules. Because the output dynamic range is as large as V
SS2
+ 0.2 V to V
DD2
−
0.2
V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line
inversion, n-line inversion, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and
even output pins respectively output gray scale voltages of differing polarity. Because of the incorporation of mini-LVDS
interface, the data transfer speed has improved and the amount of wiring on the PCB has been significantly reduced.
Remark
"mini-LVDS" is the technology with Texas Instruments applied LVDS technology and developed.
(LVDS: Low Voltage Differential Signaling)
FEATURES
•
Differential interface: CLK, gray scale data,
•
CMOS interface: STHR(L), R,/L, STB, SB, POL, O
sel
, V
sel1
, V
sel2
, SRC, ORC, RxBIAS1, RxBIAS2
•
384/360 outputs (O
sel
)
•
Capable of outputting 256 values by means of 10-by-2 external power modules (20 units) and a D/A converter
•
Logic power supply voltage (V
DD1
): 2.7 to 3.6V
•
Driver power supply voltage (V
DD2
): 10.0 to 16.5V
•
High-speed data transfer: f
CLK
= 190 MHz MAX. (internal data transfer speed when operating at V
DD1
= 2.7 V)
•
Output dynamic range: V
SS2
+ 0.2 V to V
DD2
−
0.2 V
•
Apply for dot-line inversion, n-line inversion
•
Output voltage polarity inversion function (POL)
★
ORDERING INFORMATION
Part Number
Package
TCP (TAB package)
COF (COF package)
µ
PD160010N-xxx
µ
PD160010NL-xxx
Remark
The TCP/COF’s external shape is customized. To order the required shape, please contact one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No.
S16316EJ2V0DS00 (2nd edition)
Date Published March 2004 NS CP (K)
Printed in Japan
The mark
★
shows major revised points.
2003
µ
PD160010
★
1. BLOCK DIAGRAM
CLKA
CLKB
D0A
D0B
D1A
D1B
D2A
D2B
D3A
D3B
SB
STHR
STHL
STB
D
0
to D
3
CLK
RxBIAS1, RxBIAS2
Serial to Parallel Converter
V
DD1A
V
SS1A
V
DD1D
V
SS1D
O
sel
R,/L
Logic
Controller
STHR
STHL
Bi-directional shift register
Latch
V
0
-V
19
V
DD2
D/A converter
V
SS2
POL
SRC
ORC
MODE
V
sel1
, V
sel2
Voltage follower output
--------------------------------
S
1
S
2
S
3
S
384
Remark
/xxx indicates active low signals.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S
1
•
S
2
•
S
383
•
S
384
•
POL
V
9
V
10
V
19
·····
V
0
Multi-
plexer
10
8-bit D/A converter
10
2
·····
Data Sheet S16316EJ2V0DS
µ
PD160010
3. PIN CONFIGURATION (
µ
PD160010NL-xxx:COF, Copper Foil Surface, Face-down)
VSS2
VDD2
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
(VD D 1D )
TE ST
(VSS 1D )
TE ST
(VD D 1D )
TE ST
(VSS 1D )
ORC
(V D D 1D )
S TH R
STH L
PO L
S TB
(VSS 1D )
SR C
(VD D 1D )
TE ST
TE ST
TE ST
VS S1D
V S S1A
(VS S1A)
D 0A
D 0B
(VS S1A)
D 1A
D 1B
(VS S1A)
C LK A
C LK B
(VS S1A)
D 2A
D 2B
(VS S1A)
D 3A
D 3B
V D D 1A
V D D 1D
TES T
TES T
TES T
(VD D 1D )
R xBIA S2
(V SS 1D )
R xBIA S1
(VD D 1D )
V sel1
(VSS 1D )
V sel2
(VD D 1D )
O sel
(VSS 1D )
R ,/L
(VD D 1D )
MODE
(VSS 1D )
SB
(VD D 1D )
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
VDD2
VSS2
S1
S2
S3
C opper foil
surface
S382
S383
S384
Remarks 1.
This figure does not specify the COF package.
2.
(V
DD1D
) and (V
SS1D
) is available for supply to logic input terminal. Please don’t use these pins for power
supply terminal with current.
(V
SS1A
) must be connected to analog GND on PCB.
Data Sheet S16316EJ2V0DS
3
µ
PD160010
4. PIN FUNCTIONS
(1/2)
Pin Symbol
S
1
to S
384
D0A, D0B
D1A, D1B
D2A, D2B
D3A, D3B
CLKA,
CLKB
R,/L
Shift direction
control
Shift clock
Input
(mini-LVDS)
Input
(CMOS)
Shift clock.
Refer to
Table 4−1.
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift): STHR input, S
1
→S
384
, STHL output
R,/L = L (left shift): STHL input, S
384
→S
1
, STHR output
STHR
STHL
STB
POL
Right shift start
pulse
Left shift start pulse
Latch
Polarity
Input
(CMOS)
Input
(CMOS)
SB
Bus-line set-back
Input
(CMOS)
RxBIAS1,
RxBIAS2
mini-LVDS receiver
bias voltage control
Input
(CMOS)
I/O
(CMOS)
This is the start pulse I/O pin when connected in cascade. Loading of display data
starts when a high level is read.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
Change the input mode, latched the registered data and transfer to DAC at the
rising edge. And supplied voltage to LCD pixel is output at falling edge.
Control the polarity of the output.
Input of the POL signal is allowed the setup time (t
14
) with respect to STB
’
s rising
edge.
Refer to
Table 4−3.
Change the data order of mini-LVDS input.
Refer to
Table 4−1.
Input “L” level to this pin.
This pin controls the bias current of mini-LVDS receiver circuit. Please refer to the
following table.
RxBIAS1
L
L
H
H
O
sel
Number of output
pins select pin
Input
(CMOS)
RxBIAS2
L
H
L
H
I
BIAS
I
1
(Low power)
I
2
I
3
I
4
(High power)
Pin Name
Driver
Gray scale data
I/O
Output
Input
(mini-LVDS)
Description
The D/A converted 256-gray-scale analog voltage is output.
Display data with gray-scale data (8-bit) and control signal (RST = reset).
Refer to
Table 4−1.
This pin selects the number of output pins.
O
sel
= L: 384-output mode
O
sel
= H: 360-output mode
Output pins S
181
through S
204
are invalid in 360-output mode.
SRC
ORC
MODE
Slew-rate control
Output resistance
control
Output reset control
Input
(CMOS)
Input
(CMOS)
Input
(CMOS)
SRC = H: High-slew-rate mode (large current consumption)
SRC = L: Low-slew-rate mode (small current consumption)
ORC = H: Low output resistance mode
ORC = L: High output resistance mode
MODE = H: Output reset
MODE = L: No output reset
4
Data Sheet S16316EJ2V0DS
µ
PD160010
(2/2)
Pin Symbol
V
sel1
, V
sel2
Pin Name
V
DD2
selector
I/O
Input
(CMOS)
Description
This pin controls the bias current of output amplifier.
Logic input to V
sel1
and V
sel2
have a dependence on V
DD2
and load condition and so
on. Output waveform simulation should be done before decision.
V
sel1
L
L
H
H
V
0
to V
19
V
sel2
L
H
L
H
V
DD2
Range (reference)
10.5 V TYP.
12.5 V TYP.
16.0 V TYP.
Non-assign
γ
-corrected power
supplies
−
Input the
γ
-corrected power supplies from outside. Make sure to maintain the
following relationships. During the gray scale voltage output, be sure to keep the
gray scale level power supply at a constant level.
V
DD2
−
0.2 V
≥
V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> V
8
> V
9
≥
0.5 V
DD2
0.5 V
DD2
≥
V
10
> V
11
>V
12
> V
13
> V
14
> V
15
> V
16
>V
17
> V
18
> V
19
≥
V
SS2
+ 0.2 V
V
DD1D
V
DD1A
V
DD2
V
SS1D
V
SS1A
V
SS2
TEST
Low-voltage logic
power supply
Low-voltage analog
power supply
Driver power supply
Low-voltage logic
ground
Low-voltage analog
ground
Driver ground
TEST
−
−
−
−
−
−
Input
(CMOS)
2.7 to 3.6 V
V
DD1D
and V
DD1A
should be same electric potential.
2.7 to 3.6 V
V
DD1D
and V
DD1A
should be same electric potential.
10.0 to 16.5 V
Ground for internal logic circuit.
Please wire V
SS1D
and V
SS1A
in external circuit boards
.
Ground for internal mini-LVDS receiver circuit.
Please wire V
SS1D
and V
SS1A
in external circuit boards
.
Ground for internal high voltage circuit.
Please leave these pins open in normal operation mode.
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
-V
19
in that order. Reverse this
sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.47
µ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter,
insertion of a bypass capacitor of about 0.01
µ
F is also advised between the
γ
-corrected power
supply terminals (V
0
, V
1
, V
2
,....., V
19
) and V
SS2
.
Data Sheet S16316EJ2V0DS
5
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