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UPD120N33T1B-E1-AZ

Description
1.5 V FIXED POSITIVE LDO REGULATOR, 0.9 V DROPOUT, SSO3
Categorysemiconductor    Power management   
File Size145KB,15 Pages
ManufacturerNEC ( Renesas )
Websitehttps://www2.renesas.cn/zh-cn/
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UPD120N33T1B-E1-AZ Overview

1.5 V FIXED POSITIVE LDO REGULATOR, 0.9 V DROPOUT, SSO3

UPD120N33T1B-E1-AZ Parametric

Parameter NameAttribute value
Minimum input voltage3 V
Maximum input voltage5.5 V
Number of functions1
Number of terminals3
Processing package descriptionLEAD FREE, SC-62, 3 PIN
each_compliYes
EU RoHS regulationsYes
stateTransferred
Adjustment typeFIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
Maximum voltage difference 10.9000 V
jesd_30_codeR-XSSO-F3
moisture_sensitivity_levelNOT SPECIFIED
erating_temperature,_tj_mi-40 Cel
erating_temperature,_tj_max150 Cel
Maximum output current 10.3000 A
Rated output voltage 11.5 V
Minimum output voltage 11.46 V
Maximum output voltage 11.54 V
Packaging MaterialsUNSPECIFIED
packaging shapeRECTANGULAR
Package SizeSMALL OUTLINE
eak_reflow_temperature__cel_NOT SPECIFIED
qualification_statusCOMMERCIAL
seated_height_max1.6 mm
surface mountYES
CraftsmanshipCMOS
Terminal formFLAT
Terminal spacing1.5 mm
Terminal locationSINGLE
ime_peak_reflow_temperature_max__s_NOT SPECIFIED
length4.5 mm
width2.5 mm
DATA SHEET
µ
PD120Nxx Series
THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR
(OUTPUT CURRENT: 0.3 A)
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD120Nxx series provides low-voltage output regulators with the output current capacitance of 0.3 A. The
output voltage varies according to the product (1.5 V, 1.8 V, 2.5 V, or 3.3 V). The circuit current is low due to the
CMOS structure, so the power consumption in the ICs can be reduced. Moreover, since ICs are mounted in the small
package of the
µ
PD120Nxx series, this contributes to the miniaturization of the application set.
FEATURES
Output current: 0.3 A
On-chip overcurrent protection circuit
On-chip thermal protection circuit
Small circuit operation current: 60
µ
A TYP.
APPLICATIONS
Digital TV, Audio, HDD, DVD, etc.
PIN CONFIGURATION (Marking Side)
SC-74A
SC-62
N.C.
GND
GND
5
1
2
4
3
1
2
3
OUTPUT
GND
INPUT
OUTPUT
GND
INPUT
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17145EJ2V0DS00 (2nd edition)
Date Published February 2005 NS CP(K)
Printed in Japan
2005
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