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XCV1000E-6FGG680I

Description
Field Programmable Gate Array, 6144 CLBs, 331776 Gates, 357MHz, 27648-Cell, CMOS, PBGA680, FBGA-680
CategoryProgrammable logic devices    Programmable logic   
File Size927KB,99 Pages
ManufacturerXILINX
Websitehttps://www.xilinx.com/
Environmental Compliance  
Download Datasheet Parametric View All

XCV1000E-6FGG680I Overview

Field Programmable Gate Array, 6144 CLBs, 331776 Gates, 357MHz, 27648-Cell, CMOS, PBGA680, FBGA-680

XCV1000E-6FGG680I Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerXILINX
Parts packaging codeBGA
package instructionFBGA-680
Contacts680
Reach Compliance Codeunknown
ECCN code3A991.D
maximum clock frequency357 MHz
Combined latency of CLB-Max0.47 ns
JESD-30 codeS-PBGA-B680
JESD-609 codee1
length40 mm
Humidity sensitivity level3
Configurable number of logic blocks6144
Equivalent number of gates331776
Number of entries512
Number of logical units27648
Output times512
Number of terminals680
organize6144 CLBS, 331776 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA680,39X39,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)260
power supply1.2/3.6,1.8 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height1.9 mm
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
technologyCMOS
Terminal surfaceTin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width40 mm
R
Spartan-II FPGA Family
Data Sheet
Product Specification
DS001 June 13, 2008
This document includes all four modules of the Spartan
®
-II FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS001-1 (v2.8) June 13, 2008
Introduction
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
Module 2:
Functional Description
DS001-2 (v2.8) June 13, 2008
Architectural Description
- Spartan-II Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
- Configuration Timing
Design Considerations
Module 4:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
Pin Definitions
Pinout Tables
IMPORTANT NOTE:
This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001 June 13, 2008
Product Specification
www.xilinx.com
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