ST72321B(AR7)TB/XXXE datasheet, PDF - EEWORLD Datasheet

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ST72321B(AR7)TB/XXXE: Description8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，247 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ST72321B(AR7)TB/XXXE Overview

8-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, ROHS COMPLIANT, LQFP-64

ST72321B(AR7)TB/XXXE Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	64
Reach Compliance Code	unknown
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	16 MHz
DAC channel	YES
DMA channel	NO
External data bus width
JESD-30 code	S-PQFP-G64
JESD-609 code	e3
length	10 mm
Number of I/O lines	48
Number of terminals	64
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified
ROM programmability	MROM
Maximum seat height	1.6 mm
speed	8 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	3.8 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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ST72321Bxxx-Auto

8-bit MCU for automotive with 32 to 60 Kbyte Flash/ROM,

ADC, 5 timers, SPI, SCI, I2C interface

Features

Memories

■

32 to 60 Kbyte dual voltage High Density Flash

(HDFlash) ROM with readout protection

capability. In-application programming and in-

circuit programming for HDFlash devices

■

1 to 2 Kbyte RAM

■

HDFlash endurance: 100 cycles, data retention

20 years

LQFP64

10 x 10

LQFP64

14 x 14

LQFP44

10 x 10

Up to 48 I/O ports

■

Clock, reset and supply management

■

48/32/24 multifunctional bidirectional I/O lines

■

34/22/17 alternate function lines

■

16/12/10 high sink outputs

Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

■

Clock sources: crystal/ceramic resonator

oscillators, internal RC oscillator and bypass

for external clock

■

PLL for 2x frequency multiplication

■

4 power saving modes: Halt, Active Halt, Wait

and Slow

5 timers

■

Interrupt management

■

Nested interrupt controller

■

14 interrupt vectors plus TRAP and RESET

■

Top Level Interrupt (TLI) pin on 64-pin devices

■

15/9 external interrupt lines (on 4 vectors)

1 analog peripheral (low current coupling)

■

10-bit ADC with up to 16 input ports

Table 1.

O

ST72321BR9-Auto

ST72321BAR9-Auto

ST72321BJ9-Auto

ST72321BR7-Auto

ST72321BAR7-Auto

ST72321BJ7-Auto

ST72321BR6-Auto

ST72321BAR6-Auto

ST72321BJ6-Auto

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Main clock controller with Real-time base,

Beep and Clock-out capabilities

■

Configurable watchdog timer

■

Two 16-bit timers with 2 input captures, 2

output compares, external clock input on 1

timer, PWM and pulse generator modes

■

8-bit PWM auto-reload timer with 2 input

captures, 4 PWM outputs, output compare and

time base interrupt, external clock with event

detector

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3 communications interfaces

SPI synchronous serial interface

■

SCI asynchronous serial interface

2

■

I C multimaster interface

Development tools

■

Full HW/SW development pkg, ICT capability

Device summary

Prog. memory

Flash/ROM

60 Kbytes

Flash/ROM

48 Kbytes

Flash/ROM

32 Kbytes

RAM (stack)

2048 (256)

bytes

1536 (256)

bytes

1024 (256)

bytes

3.8 to 5.5V

Up to

-40 to 125°C

Oper. voltage Temp. range

Package

LQFP64

LQFP44

LQFP64

LQFP44

LQFP64

LQFP44

14x14

10x10

10x10

14x14

10x10

10x10

14x14

10x10

10x10

October 2007

Rev 1

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www.st.com

1

Contents

ST72321Bxxx-Auto

Contents

1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.1

1.2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Differences between ST72321B-Auto and ST72321B datasheets . . . . . . 20

1.2.1

1.2.2

1.2.3

Principal differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Minor content differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Editing and formatting differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2

Package pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.1

2.2

Package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3

4

Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3.1

Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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5.1

5.2

5.3

Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Condition code (CC) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Stack pointer (SP) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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ST72321Bxxx-Auto

Contents

6

Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1

6.2

6.3

6.4

6.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.5.1

6.5.2

6.5.3

6.5.4

6.5.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

External power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Internal low voltage detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . 48

Internal watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.6

System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

System Integrity (SI) Control/Status register (SICSR) . . . . . . . . . . . . . . 53

7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.1

7.2

7.3

7.4

7.5

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.5.1

7.5.2

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7.6

8.1

8.2

8.3

8.4

External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.6.1

7.6.2

I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . 64

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CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt software priority registers (ISPRx) . . . . . . . . . . . . . . . . . . . . . . 60

Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Active Halt and Halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3/247

Contents

8.4.1

8.4.2

ST72321Bxxx-Auto

Active Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.1

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.2.1

9.2.2

9.2.3

Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.3

9.4

9.5

I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

10

Watchdog timer (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . 85

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.9.1

11

Main clock controller with real-time clock and beeper (MCC/RTC) . . 87

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11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Main clock controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

11.8.1

MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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ST72321Bxxx-Auto

11.8.2

Contents

MCC beep control register (MCCBCR) . . . . . . . . . . . . . . . . . . . . . . . . . 90

12

PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

12.1

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

12.2.1

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.2.7

12.2.8

12.2.9

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Counter and prescaler initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Output compare and time base interrupt . . . . . . . . . . . . . . . . . . . . . . . . 95

External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 95

Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

12.3

ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

12.3.7

Control/status register (ARTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Counter access register (ARTCAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Auto-reload register (ARTARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PWM control register (PWMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Duty cycle registers (PWMDCRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Input capture control / status register (ARTICCSR) . . . . . . . . . . . . . . . 101

Input capture registers (ARTICRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

13

16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

13.1

13.2

13.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

13.3.1

13.3.2

13.3.3

13.3.4

13.3.5

13.3.6

13.3.7

Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

One Pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

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Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5/247

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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