DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC8100GR
SILICON UP/DOWN CONVERTERS IC
FOR 800 MHz to 900 MHz MOBILE COMMUNICATIONS
DESCRIPTION
µ
PC8100GR is a silicon monolithic integrated circuit designed as up/down converters for 800 MHz to 900 MHz mobile
communications, mainly CT2. This IC consists of upconverter and downconverter, which are packaged in 20 pin SSOP.
Quadrature modulator IC (
µ
PC8101GR) is also available as for kit-use with this IC. So, these pair devices contribute to
make RF block small, high-performance and low power-consumption.
This product is manufactured using NEC’s 20 GHz f
T
NESAT
™
III
silicon bipolar process. This process uses silicon nitride
passivation film and gold electrodes. These materials can protect chip surface from external pollution and prevent corrosion
and migration. Thus, this product has excellent performance, uniformity and reliability.
FEATURES
• Operating frequency – f
RF
= 800 MHz to 900 MHz, f
IF
= 50 MHz to 150 MHz, f
Lo
= 650 MHz to 1 050 MHz
• Upconverter and downconverter are integrated in 1 chip.
• 20 pin SSOP suitable for high-density surface mounting.
• Wide operating voltage V
CC
= 2.7 to 4.5 V
• Equipped with Power Save Function.
• Excellent linearity
APPLICATIONS
• Typical application – Digital cordless phone CT2.
• Further application – Digital cellular, etc.
ORDERING INFORMATION
PART NUMBER
PACKAGE
20 pin plastic SSOP
(225 mil)
SUPPLYING FORM
Embossed tape 12 mm wide. QTY 2.5 kp/Reel.
Pin 1 indicates roll-in direction of tape.
µ
PC8100GR-E2
Remark
To order evaluation samples, please contact your local NEC sales office. (Order number:
µ
PC8100GR)
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10817EJ3V0DS00 (3rd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995,1999
µ
PC8100GR
INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS
(Top View)
20
19
18
17
16
15
14
13
12
11
REG. REG.
1
2
3
4
5
6
7
8
9
10
1. GND
1
2. RF BYPASS
3. RF INPUT
2
4. PEAKING OUT
3
5. P/S (for DOWN CONV.)
4
6. P/S (for UP CONV.)
5
7. V
CC
(for UP CONV.)
8. RF OUTPUT
6
9. GND
7
10. MIX OUTPUT1
8
11. MIX OUTPUT2
12. GND
9
13. IF BYPASS
10
14. IF INPUT
15. OSC INPUT (for UP CONV.)
16. OSC BYPASS (for UP CONV.)
17. OSC BYPASS (for DOWN CONV.)
18. OSC INPUT (for DOWN CONV.)
19. V
CC
(for DOWN CONV.)
20. IF OUTPUT
20
19
18
17
16
15
14
13
12
11
2
Data Sheet P10817EJ3V0DS00
µ
PC8100GR
PIN EXPLANATION
PIN
NO.
1
ASSIGNMENT
APPLIED
VOLTAGE (V)
0.0
PIN VOLTAGE
(V)
–
FUNCTION AND APPLICATION
EQUIVALENT CIRCUIT
GND
Ground for downconverter.
Must be connected to the system ground
with minimum inductance. Ground pat-
tern on the board should be formed as
wide as possible.
(Track length should be kept as short as
possible.)
2
RF bypass
–
1.1
Bypass of RF input for downconverter.
V
CC
3
RF input
–
0.9
This pin is RF input for downconverter
designed as double balanced mixer.
This high-impedance input should be
matched with external chip inductor. (eg
4.7 nH).
3
4
REG.
REG.
2
4
Peaking out
–
0.12
Open emitter pin of low noise amplifier.
Grounded with capacitor (eg 3 pF) and
register (eg 22
Ω)
serially.
5
Power-save pin
for
downconverter
0 to 4.5
–
This pin can control downconverter’s
ON/OFF operation with bias as follows;
Bias: V
V
PS
≥1.8
0 to 1.0
Operation
ON
OFF
5
6
Power-save pin
for
upconverter
V
PS
0 to 4.5
–
This pin can control upconverter’s ON/
OFF operation with bias as follows;
Bias: V
≥1.8
0 to 1.0
Operation
ON
OFF
or
6
7
V
CC
for
upconverter
2.7 to 4.5
–
Supply voltage for upconverter.
Must be connected bypass capacitor
(e.g 1 000 pF) to minimize ground im-
pedance.
REG.
8
8
RF output
same as
V
CC
through
intactor
–
F output from upconverter.
Connect the V
CC
through inductor (eg 15
nH).
9
GND
0.0
–
Ground for RF amplifier of upconverter.
Data Sheet P10817EJ3V0DS00
3
µ
PC8100GR
PIN EXPLANATION
PIN
NO.
10
11
ASSIGNMENT
MIX OUT 1
MIX OUT 2
PIN VOLTAGE
(V)
2.3
2.3
FUNCTION AND APPLICATION
Mixer output from upconverter.
Mixer output from upconverter.
10 and 11 pins should be externally
equipped with tank circuit of inductor (eg
4.7 nH) and capacitor (eg 3.5 pF).
EQUIVALENT CIRCUIT
10
12
GND
0*
Ground for oscillator buffer amplifier and
mixer of upconverter.
Must be connected to the system ground
with minimum inductance. Ground
pattern on the board should be formed
as wide as possible.
(Track length should be kept as short as
possible.)
13
14
IF bypass
IF input
1.03
1.03
Bypass of IF input for upconverter.
This pin is IF input for upconverter
designed as double balanced mixer.
This high-impedance input should be
externally equipped with matching circuit
of inductor (eg 220 nH) and capacitor
(eg 1.5 pF).
15
OSC input
(for upconverter)
16
OSC bypass
(for upconverter)
17
OSC bypass
(for down-
converter)
18
OSC input
(for down-
converter)
19
V
CC
supply for
for down-
converter
2.7 to 4.5*
1.85
Local oscillator input for down-
converter. Required for matching with
register 51
Ω.
Supply voltage for downconverter.
It must be connected bypass capacitor
(e.g 1 000 pF) to minimize ground
impedance.
20
IF output
1.45
IF output from downconverter.
1.85
1.8
1.8
Local oscillator input for upconverter. Re-
quired for matching with register 51
Ω.
Bypass of local oscillator input for
upconverter.
Bypass of local oscillator input for
downconverter.
11
V
CC
14
13
REG.
V
CC
15 , 18
16 , 17
V
CC
20
*
Externally supply voltage
4
Data Sheet P10817EJ3V0DS00
µ
PC8100GR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation
of package allowance
Operating Temperature
Storage Temperature
T
opt
T
stg
V
CC
P
D
T
A
= +25
°C
Mounted on 50
×
50
×
1.6 mm double copper
clad epoxy glass board at T
A
= +70
°C
–20 to +70
–65 to +150
°C
°C
5.0
530
V
mW
RECOMMENDED OPERATING CONDITIONS
PARAMETERS
Supply Voltage
Operating Temperature
SYMBOL
V
CC
T
opt
MIN.
2.7
–20
TYP.
3.0
+25
MAX.
4.5
+70
UNIT
V
°C
ELECTRICAL CHARACTERISTICS (T
A
= +25
°
C, V
CC
= 2.7 V, Z
L
= Z
S
= 50
Ω,
unless otherwise specified;
V
P/S
≥
1.8 V)
PARAMETERS
UPCONVERTER BLOCK
*
1
Circuit current
Conversion gain
RF output level
Noise figure
Local leakage at RF
out
IF leakage at RF
out
Circuit current in power-save mode
*
3
Power-save control voltage
I
CC
CG
P
RFout
NF
Lo
rf
IF
rf
I
CC
(P/S)
V
P/S
(ON)
V
P/S
(OFF)
Rise up time
DOWNCONVERTER BLOCK
*
2
Circuit current
Conversion gain
IF output level
3rd order intermodulation distortion
I
CC
CG
P
IFout
IM3
8.0
15.0
–4.5
–45.0
15.0
18.0
–2.0
–49.0
22.0
23.0
mA
dB
dBm
dBc
No input signal
P
RFin
= –40 dBm
P
RFin
= –10 dBm, 50
Ω
load
f
RFin
1 = 866.4 MHz, P
RFin
1 = –40 dBm
f
RFin
2 = 866.8 MHz, P
RFin
2 = –40 dBm
Noise figure
Circuit current in power-save mode
*
3
Power-save control voltage
NF
I
CC
(P/S)
V
P/S
(ON)
V
P/S
(OFF)
Rise up time
T
up
2.5
1.8
7.5
220
10
350
4.5
1.0
5.0
dB
DSB mode
5PIN(P/S)
≤
1.0 V
T
up
2.5
1.8
13.0
17.5
0
25.0
20.5
3
13
–25.0
–12.0
220
18
–10.0
–5.0
350
4.5
1.0
5.0
35.0
25.5
mA
dB
dBm
dB
dBm
dBm
No input signal
P
IFin
= –40 dBm
P
IFin
= –10 dBm, 50
Ω
load
DSB mode
P
IFin
= –10 dBm
P
IFin
= –10 dBm
6PIN(P/S)
≤
1.0 V
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
µ
A
V
V
µ
s
µ
A
V
V
µ
s
*1
: f
IFin
= 150.05 MHz, f
RFout
= 864.05 to 868.05 MHz
f
Loin
= 1014.10 to 1018.1 MHz (–9 dBm)
*2
: f
RFin
= 864.05 to 868.05 MHz, f
IFout
= 150.05 MHz
f
Loin
= 1014.10 to 1018.1 MHz (–9 dBm)
*3
: Circuit current in power-save mode is total value of upconverter+downconverter
Data Sheet P10817EJ3V0DS00
5
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