AN1004
Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
HIGH-PERFORMANCE PRODUCTS
About LVDS
As the bandwidth increases in Telecom / Datacom
and even in consumer / commercial applications ,
the high speed, low power, noise, and cost of LVDS
signal broaden the scope of its application beyond
the traditional technologies such as ECL / PECL.
LVDS (Low Voltage Differential Signaling) are differ-
ential signals with typical 350 mV swing and a DC
offset of 1.2V. When moving signals from box-to-
box or board-to-board (i.e. flat panel display). LVDS
is the right solution because it generates less noise,
consumes less power and it is very cost effective.
Figure 1 shows different voltage levels for different
types of signals.
Interfacing LVDS with PECL and LVPECL
Signal level translation between PECL / LVPECL to
LVDS can be achieved using resistor divider network;
however, when using discrete logic the signal volt-
age level would shift with respect to supply voltage
and ambient temperature fluctuation. In turn, this
will diminish the signal integrity and cause duty cycle
distortion. To avoid such problems, Semtech has
designed a fully integrated IC devices that translate
PECL / LVPECL signal into LVDS and LVDS to PECL /
LVPECL type signals. Refer to table 1 for a list of
these devices. Semtech also offers a fully integrated
receiver / driver device with true LVDS inputs and
outputs (SK1303) in an 8-lead SOIC and MSOP pack-
ages.
LVDS signals can easily be terminated with a 100
W
resistor across the differential LVDS outputs. Most
devices with LVDS I / O provide the 100W resistor
internally at its inputs to minimize component count
(i.e. SK1301). Figure 2 is an example of LVDS out-
put termination. For PECL / LVPECL output termina-
tion refer to application note AN1003.
LVDS
HSTL
PECL
LVPECL
+
0V
NC
ECL /LVECL
1
8
V
CC
-
Figure 1: Relative differences among various I/O standards
D
2
100
Ω
7
Q
LVDS
Note:
HSTL (High-Speed Transceiver Logic) signals are used in computing de-
sign applications such as memory drivers and high-speed CPU-to-Memory
D
*
3
6
Q*
RT
RT
NC
interfacing.
4
SK1301
5
V
EE
VTT
Figure 2: LVDS Termination
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AN1004
HIGH-PERFORMANCE PRODUCTS
Interfacing LVDS with PECL and LVPECL
(con’d)
Device
SK1300
SK1301
Function
PECL / LVPECL to LVDS Translator
LVDS to PECL / LVPECL Translator
Package
Type
8 PIN SOIC
/ MSOP
8 PIN SOIC
/ MSOP
Operating
Voltage
3.0V to
5.5V
3.0V to
5.5V
Table 1
LVDS with PECL / LVPECL Signal Distribution
Figure 3 is a good example showing how we can
fan-out LVDS signal using PECL / LVPECL devices.
SK10/100EL11W, a 1:2 fan-out buffer, is used as
an example to fan-out the LVDS signal into either
PECL or LVPECL signals. It is important to mention
that SK100EL11W has PECL / LVPECL type inputs,
but with its extended input common mode range it
can accept LVDS type signal without having to go
through any kind of signal translation. This kind of
feature makes clock distribution or generation de-
vices ideal to directly interface with LVDS signals
and provide PECL / LVPECL type outputs. Table 2
depicts some of the devices that can directly ac-
cept LVDS signals.
V
CC
To PECL / LVPECL Devices
LVDS
100Ω
To PECL / LVPECL Devices
SK10/100EL11W
Figure 3: LVDS to PECL / LVPECL
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AN1004
HIGH-PERFORMANCE PRODUCTS
LVDS with PECL / LVPECL Signal Distribution
(con’d)
Device
SK10/100EL11W
SK10/100EL14W
SK10/100EL15W
SK10/100EL38W
SK10/100EL39W
SK10/100EL57W
SK10/100EL91W
SK10/100LVEL111/E
SK15XX
SK19XX
SK44XX
Function
1:2 Differential Fanout Buffer
1:5 Clock Distribution Chip
1:4 Clock Distribution
Package
Type
8 PIN
SOIC/MSOP
20 PIN SOIC
16 PIN SOIC
20 PIN SOIC
20 PIN SOIC
16 PIN SOIC
20 PIN SOIC
20 PIN PLCC
32 PIN TQFP
32 PIN TQFP
32 PIN TQFP
Operating
Voltage
3.0V to 5.5V
3.0V to 5.5V
3.0V to 5.5V
3.0V to 5.5V
3.0V to 5.5V
3.0V to 5.5V
-5.0V to -3.0V/
3.0V to 5.5V
3.0V to 3.8V
3.0V to 5.5V
3.3V to 5.2V
3.3V to 5.2V
¸
2
,
¸
4/6 Clock Generation Chip
¸
2/4
,
¸
4/6 Clock Generation Chip
4:1 Differential Multiplexer
Triple PECL to ECL / LVECL and LVPECL to ECL
/ LVECL Translator
1:9 Differential LVECL / LVPECL Clock Driver
1:5 Signal Distribution
1:9 Signal Distribution
Quad Buffer/Receiver
Table 2
Interfacing LVDS with ECL and LVECL
Since LVDS signals are in the positive region, they can
interface with ECL / LVECL signal in two different ways.
The first method is to simply use SK10 / 100EL91W,
triple PECL to ECL / LVECL and LVPECL to ECL / LVECL
translator, to convert the LVDS signal into ECL or LVECL
type signal. The extended input common mode range of
SK10 / 100EL91W will allow the LVDS signal to directly
interface with the inputs of SK10 / 100EL91W. Figure 4
shows LVDS interface to ECL / LVECL using SK10 /
100EL91W, please note that for ECL / LVECL output ter-
mination refer to the application note AN1003.
3.3V
3.3V
The alternative method would be the capacitive coupling
of the LVDS to ECL / LVECL signals. Figure 5 shows
such interface with ECL devices that provide a VBB out-
put. The 100 K
W
resistor is to prevent the outputs from
oscillating during null state signal conditions. If the
VBB output is not provided by the ECL device, Thevenin
equivalent parallel termination scheme can be used to
reset the threshold to the inputs of the ECL / LVECL
device, as shown in Figure 6. In the board layout, both
the capacitors and the resistors must be as close to
the ECL / LVECL device as possible.
V
CC
10pF
100Ω
Zo = 50Ω
10pF
1kΩ
1kΩ
100KΩ
VCC = 0V
Zo = 50Ω
LVDS
Zo = 50Ω
100Ω
EL91W
50Ω
-3.3V/-5.0V
-3.3V/-5.0V
ECL /
LVECL
Zo = 50Ω
LVDS
ECL
V
BB
VTT = VCC - 2.0V
Figure 4: LVDS tp ECL/LVECL
10nF
Figure 5: Cacapitive Coupling of LVDS to ECL
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AN1004
HIGH-PERFORMANCE PRODUCTS
Interfacing LVDS with ECL and LVECL
(con’d)
VCC
R1
R1
Zo = 50Ω
LVDS
100Ω
10pF
Zo = 50Ω
ECL
10pF
R2
R2
VEE
Figure 6: Capacitive Coupling of LDVS to ECL with Different Termination
Examples: VCC = GND, VEE = -5.0V: R1 = 1.2 KW and R2 = 3.4KW
VCC = GND, VEE = -3.3V: R1 = 680W and R2 = 1 KW
Interfacing ECL / LVECL with LVDS
The ECL / LVECL outputs are emitter follower out-
puts; therefore, they need a DC path to VEE. When
capacitive coupled, the ECL outputs need pull-down
resistors to VEE as shown in Figure 7. The Thevenin
equivalent parallel termination resistors represent
the termination of the transmission line Zo = R1 ||
R2 and generates a DC level of 1.2V (typical) which
is the threshold of the LVDS signal.
VCC = 3.3V
R1
Zo = 50Ω
ECL
10pF
R1
140Ω
Zo = 50Ω
RT
VEE
RT
100Ω
10pF
R2
R2
LVDS
80Ω
Figure 7: ECL / LVECL to LVDS
Note:
R
T
= 150W for a 3.3V system and
R
T
= 270W for a 5.0V system.
Contact Information
Division Headquarters
10021 Willow Creek Road
San Diego, CA 92131
Phone: (858) 695-1808
FAX:
(858) 695-2633
Semtech Corporation
High-Performance Products Division
Marketing Group
1111 Comstock Street
Santa Clara, CA 95054
Phone: (408) 566-8776
FAX: (408) 727-8994
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