Standard ICs
LCD driver for segment-type LCDs
BU9728AKV
The BU9728AKV is a segment-type LCD system driver which can accommodate microcomputer control and a serial
interface. An internal 4-bit common output and LCD drive power supply circuit enable configuration of a display sys-
tem at low cost.
•
Applications car audio systems, telephones
Movie projectors,
•
Features
1) Serial interface. (8-bit length)
2) Display RAM: Internal, 128 bits. (up to 128 seg-
ments can be displayed)
3) Internal power supply circuit for LCD drive.
4) Display duty: 1 / 4
5) Can be driven with low voltage and low current dissi-
pation.
•
Absolute maximum ratings (Ta = 25°C, V
Parameter
Power supply voltage 1
Power supply voltage 2
Power dissipation
Operating temperature
Storage temperature
SS
= 0V)
Limits
– 0.3 ~ + 7.0
– 0.3 ~ + V
DD
400
∗
– 20 ~ + 75
– 55 ~ + 125
Unit
V
V
mW
°C
°C
Symbol
V
DD
V
LCD
Pd
Topr
Tstg
over 25°C .
∗
Reduced by 4.0mW for each increase in Ta of 1°C
•
Recommended operating conditions (Ta = 25°C, V
Parameter
Power supply voltage 1
Power supply voltage 2
(V
DD
- V
3
)
Oscillation frequency
SS
= 0V)
Max.
5.5
V
DD
—
Unit
V
V
kHz
Conditions
—
The following relationship should
be maintained: V
DD
V
1
V
2
V
3
R
f
= 470kΩ
V
SS
.
Symbol
V
DD
V
LCD
f
OSC
Min.
2.5
0
—
Typ.
—
—
36
1
Standard ICs
BU9728AKV
•
Block diagram
V
DD
LCD Driver
Bias Circuit
RESET
V
1
V
2
V
3
V
SS
SD
SCK
C/D
CS
SEG
0
Serial
Interface
Address
Counter
Display Data RAM
(DD RAM)
LCD
Segment
Driver
32bits
SEG
1
SEG
31
Command / Data
Register
LCD
Common
Driver
4bits
COM
0
COM
1
COM
2
COM
3
Command
Decoder
Timing
Generator
Common
Counter
OSC
1
SEG
19
SEG
18
SEG
17
SEG
16
SEG
15
SEG
14
SEG
13
SEG
12
SEG
11
SEG
10
SEG
9
SEG
20
SEG
21
SEG
22
SEG
23
SEG
24
SEG
25
SEG
26
SEG
27
SEG
28
SEG
29
SEG
30
SEG
31
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
23
22
21
20
19
18
17
16
15
14
13
9 10 11 12
SEG
8
•
Pin assignments
OSC
2
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
RESET
COM
3
COM
2
COM
1
BU9728AKV
C/D
2
COM
0
V
DD
SD
OSC
1
OSC
2
SCK
V
SS
CS
V
1
V
2
V
3
Standard ICs
BU9728AKV
Pin NO.
1
2
3~5
6
7
8
I/O
I
O
—
—
—
I
Function
Input / output pins for the internal oscillator. Resistance is connected between
these pins when the internal clock is running. When an external clock is
running, the clock is input from OSC
1
and OSC
2
is left open.
These are power supply pins for LCD drive.
The following relationship must be satisfied: V
DD
This is the V
SS
power supply pin.
This is the V
DD
power supply pin.
This is the shift clock input pin for serial data. The contents of the SD pin are
read one bit at a time at the rising edge of SCK.
This is the serial data input pin, used to input display data and commands.
Display data is displayed when this is "1" and not displayed when it is "0".
This is the chip select signal input pin. When this pin is LOW, SD input can be
received. The SCK counter is reset when the CS pin goes from HIGH to LOW.
This signal detects whether the SD input is command or display data. If the pin
is LOW at the rising edge of the 8th SCK pulse, the input is recognized as
display data, and if HIGH, the input is recognized as command data.
These are the common output pins for LCD drive. They are connected to the
LCD panel commons.
This is the reset input pin. When this pin is LOW, the BU9728AKV is initialized.
It resets the address counter and turns the display off.
These are the segment output pins for LCD drive. They are connected to the
LCD panel segments.
V
1
V
2
V
3
V
SS
(Low) .
•
Pin descriptions
Pin name
OSC
1
OSC
2
V
1
~ V
3
V
SS
V
DD
SCK
SD
9
I
CS
10
I
C/D
COM
0
11
I
12 ~ 15
COM
3
RESET
SEG
0
17 ~ 48
SEG
31
16
O
I
O
•
Input / output equivalent circuits
Pin name I / O
SD
SCK
C/D
CS
I
V
DD
IN
GND
Equivalent Circuit
Pin name I / O
SEG
0
SEG
31
OUT
Equivalent Circuit
V
LCD
O
~
V
LCD
COM
0
COM
3
~
GND
OSC
1
OSC
2
—
OSC
1
VDD
OSC
2
GND
RESET
I
IN
V
DD
GND
3
Standard ICs
BU9728AKV
•
Electrical characteristics otherwise noted, V
DC characteristics (unless
Parameter
Input high level voltage
Input low level voltage
LCD driver ON resistance
∗
1
Input low level current 1
Input low level current 2
Input high level current
Input capacitance
DD
= 2.5 ~ 5.5V, V
SS
= 0V, Ta = 25°C)
Max.
V
DD
0.2
×
V
DD
30
100
2
—
—
1
80
250
Unit
V
V
kΩ
µA
µA
µA
pF
µA
µA
µA
Conditions
—
—
∆V
ON
=
0.1V
V
IN
=
0V
V
IN
=
0V
V
IN
=
V
DD
—
In wait state
∗
2
When display is operating
∗
3
During access operation
∗
4
Symbol
V
IH1
V
IL1
R
ON
I
IL1
I
IL2
I
IH
C
IN
Min.
0.8
×
V
DD
0
—
—
—
–2
—
—
Typ.
—
—
—
—
—
—
5
0.05
40
100
Pin
OSC
1
, SD, SCK, C / D, CS
RESET
SEG
0 ~ 31
, COM
0 ~ 3
RESET
OSC
1
, SD, SCK, C / D, CS
OSC
1
, SD, SCK, C / D, CS,
RESET
SD, SCK, C / D, CS
Current dissipation
I
DD
—
—
V
DD
∗
1 Internal power supply impedance is not included in the LCD driver ON resistance.
∗
2 All inputs, including V
3
= 0V and OSC
1
, are fixed at either V
DD
or V
SS
.
∗
3 Except for V
3
= 0V, Rf = 470kΩ , and OSC
1
, all inputs are fixed at either V
DD
or V
SS
.
∗
4 V
3
= 0V, Rf = 470kΩ , f = 200kHz
SCK
AC characteristics (unless otherwise noted, V
DD
= 2.5 ~ 5.5V, V
SS
= 0V, Ta = 25°C)
Parameter
SCK rise time
SCK fall time
SCK cycle time
Command wait time
SCK pulse width "H"
SCK pulse width "L"
Data setup time
Data hold time
CS pulse width "H"
CS pulse width "L"
CS set-up time
CS hold time
C / D set-up time
C / D hold time
C / D - CS time
∗
5
C / D - SCK time
∗
5
Symbol
t
TLH
t
THL
t
CYC
t
WAIT
t
WH1
t
WL1
t
SU1
t
H1
t
WH2
t
WL2
t
SU2
t
H2
t
SU3
t
H3
t
CCH
t
SCH
Min.
—
—
800
800
300
300
100
100
300
6400
100
100
100
100
100
100
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
100
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
—
—
—
—
—
—
—
—
—
—
—
—
—
Use rise for 8th CK of SCK as standard
Use CS riss as standard
Use rise for 8th CK of SCK as standard
∗
5
Only one (either one) of the conditions needs to be satisfied.
4
Standard ICs
BU9728AKV
•
Timing charts
CS
t
SU2
t
CYC
t
WH1
SCK
t
WL2
t
WH2
t
H2
t
WL1
t
TLH
t
SU1
SD
t
H1
t
THL
t
CCH
t
SCH
t
SU3
t
H3
C/D
Fig.1 Interface timing
t
CYC
t
WAIT
SCK
SD
D7
D6
D0
D7
Fig.2 Command cycle
format
•
Datadata is 4-line data transmitted in synchronization with the clock. Serial data with a bit length of 8 bits is input in
Serial
synchronization with SCK. If C / D is HIGH at the rising edge of the 8
×
nth SCK clock pulse, the serial data is recog-
nized as command data, and if C / D is LOW, the serial data is recognized as display data. Serial data is input in
sequential order, starting from the MSB.
5
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