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PEMD18

Description
Small Signal Bipolar Transistor, 0.1A I(C), 50V V(BR)CEO, 2-Element, NPN and PNP, Silicon
CategoryDiscrete semiconductor    The transistor   
File Size913KB,16 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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PEMD18 Overview

Small Signal Bipolar Transistor, 0.1A I(C), 50V V(BR)CEO, 2-Element, NPN and PNP, Silicon

PEMD18 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionSMALL OUTLINE, R-PDSO-F6
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresBUILT IN BIAS RESISTOR RATIO 2.1
Maximum collector current (IC)0.1 A
Collector-emitter maximum voltage50 V
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE)50
JESD-30 codeR-PDSO-F6
JESD-609 codee3
Humidity sensitivity level1
Number of components2
Number of terminals6
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Polarity/channel typeNPN AND PNP
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin (Sn)
Terminal formFLAT
Terminal locationDUAL
Maximum time at peak reflow temperature30
transistor applicationsSWITCHING
Transistor component materialsSILICON

PEMD18 Preview

PEMD18; PUMD18
NPN/PNP resistor-equipped transistors;
R1 = 4.7 k, R2 = 10 k
Rev. 2 — 21 December 2011
Product data sheet
1. Product profile
1.1 General description
NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted
Device (SMD) plastic packages.
Table 1.
Product overview
Package
NXP
PEMD18
PUMD18
SOT666
SOT363
JEITA
-
SC-88
PNP/PNP
complement
PEMB18
PUMB18
NPN/NPN
complement
PEMH18
PUMH18
Package
configuration
ultra small and flat
lead
very small
Type number
1.2 Features and benefits
100 mA output current capability
Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
AEC-Q101 qualified
1.3 Applications
Low current peripheral driver
Control of IC inputs
Replaces general-purpose transistors in digital applications
1.4 Quick reference data
Table 2.
Symbol
V
CEO
I
O
R1
R2/R1
Quick reference data
Parameter
collector-emitter voltage
output current
bias resistor 1 (input)
bias resistor ratio
Conditions
open base
Min
-
-
3.3
1.7
Typ
-
-
4.7
2.1
Max
50
100
6.1
2.6
Unit
V
mA
k
Per transistor; for the PNP transistor (TR2) with negative polarity
NXP Semiconductors
PEMD18; PUMD18
NPN/PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k
2. Pinning information
Table 3.
Pin
1
2
3
4
5
6
Pinning
Description
GND (emitter) TR1
input (base) TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
output (collector) TR1
1
2
3
001aab555
TR1
R2
R1
R1
R2
TR2
Simplified outline
6
5
4
Graphic symbol
6
5
4
1
2
3
006aaa143
3. Ordering information
Table 4.
Ordering information
Package
Name
PEMD18
PUMD18
-
SC-88
Description
plastic surface-mounted package; 6 leads
plastic surface-mounted package; 6 leads
Version
SOT666
SOT363
Type number
4. Marking
Table 5.
PEMD18
PUMD18
[1]
* = placeholder for manufacturing site code
Marking codes
Marking code
[1]
6B
T5*
Type number
PEMD18_PUMD18
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 December 2011
2 of 16
NXP Semiconductors
PEMD18; PUMD18
NPN/PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
V
I
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage TR1
positive
negative
input voltage TR2
positive
negative
I
O
I
CM
P
tot
output current
peak collector current
total power dissipation
PEMD18 (SOT666)
PUMD18 (SOT363)
Per device
P
tot
total power dissipation
PEMD18 (SOT666)
PUMD18 (SOT363)
T
j
T
amb
T
stg
[1]
[2]
Conditions
open emitter
open base
open collector
Min
-
-
-
-
-
-
-
-
Max
50
50
7
+20
7
+7
20
100
100
Unit
V
V
V
V
V
V
V
mA
mA
Per transistor; for the PNP transistor (TR2) with negative polarity
single pulse;
t
p
1 ms
T
amb
25
C
[1][2]
[1]
-
-
-
200
200
mW
mW
T
amb
25
C
[1][2]
[1]
-
-
-
65
65
300
300
150
+150
+150
mW
mW
C
C
C
junction temperature
ambient temperature
storage temperature
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
Reflow soldering is the only recommended soldering method.
PEMD18_PUMD18
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 December 2011
3 of 16
NXP Semiconductors
PEMD18; PUMD18
NPN/PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k
400
P
tot
(mW)
300
006aac749
200
100
0
-75
-25
25
75
125
175
T
amb
(°C)
FR4 PCB, standard footprint
Fig 1.
Per device: Power derating curve for SOT363 (SC-88) and SOT666
6. Thermal characteristics
Table 7.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to ambient
PEMD18 (SOT666)
PUMD18 (SOT363)
Per device
R
th(j-a)
thermal resistance from
junction to ambient
PEMD18 (SOT666)
PUMD18 (SOT363)
[1]
[2]
Conditions
in free air
[1][2]
[1]
Min
Typ
Max
Unit
Per transistor
-
-
-
-
625
625
K/W
K/W
in free air
[1][2]
[1]
-
-
-
-
417
417
K/W
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Reflow soldering is the only recommended soldering method.
PEMD18_PUMD18
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 December 2011
4 of 16
NXP Semiconductors
PEMD18; PUMD18
NPN/PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k
10
3
duty cycle = 1
Z
th(j-a)
(K/W)
10
2
0.1
0.05
0.02
0.01
0.75
0.5
0.33
0.2
006aac751
10
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 2.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for
PEMD18 (SOT666); typical values
006aac750
10
3
duty cycle = 1
Z
th(j-a)
(K/W)
10
2
0.1
0.05
0.02
10
0
0.75
0.5
0.33
0.2
0.01
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 3.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for
PUMD18 (SOT363); typical values
PEMD18_PUMD18
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 21 December 2011
5 of 16

PEMD18 Related Products

PEMD18 PUMD18 934058903115
Description Small Signal Bipolar Transistor, 0.1A I(C), 50V V(BR)CEO, 2-Element, NPN and PNP, Silicon Small Signal Bipolar Transistor, 0.1A I(C), 50V V(BR)CEO, 2-Element, NPN and PNP, Silicon Small Signal Bipolar Transistor, 0.1A I(C), 50V V(BR)CEO, 2-Element, NPN and PNP, Silicon
Is it Rohs certified? conform to conform to conform to
Maker Nexperia Nexperia Nexperia
package instruction SMALL OUTLINE, R-PDSO-F6 SMALL OUTLINE, R-PDSO-G6 SMALL OUTLINE, R-PDSO-G6
Reach Compliance Code compliant compliant compliant
ECCN code EAR99 EAR99 EAR99
Other features BUILT IN BIAS RESISTOR RATIO 2.1 BUILT IN BIAS RESISTOR RATIO 2.1 BUILT IN BIAS RESISTOR RATIO 2.1
Maximum collector current (IC) 0.1 A 0.1 A 0.1 A
Collector-emitter maximum voltage 50 V 50 V 50 V
Configuration SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE) 50 50 50
JESD-30 code R-PDSO-F6 R-PDSO-G6 R-PDSO-G6
JESD-609 code e3 e3 e3
Humidity sensitivity level 1 1 1
Number of components 2 2 2
Number of terminals 6 6 6
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type NPN AND PNP NPN AND PNP NPN AND PNP
surface mount YES YES YES
Terminal surface Tin (Sn) Tin (Sn) Tin (Sn)
Terminal form FLAT GULL WING GULL WING
Terminal location DUAL DUAL DUAL
transistor applications SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON
Maximum operating temperature 150 °C 150 °C -
Peak Reflow Temperature (Celsius) 260 260 -
Certification status Not Qualified Not Qualified -
Maximum time at peak reflow temperature 30 30 -
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