ADVANCE
16, 32 MEG x 72
DDR REGISTERED SDRAM DIMMs
DDR SDRAM
DIMM MODULE
FEATURES
• 184-pin, dual in-line memory modules (DIMM)
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce
loading
• Utilizes 100 MHz and 133 MHz DDR SDRAM
components
• ECC-optimized pinout
• 128MB (16 Meg x 72), 256MB (32 Meg x 72)
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• V
DDSPD
= +2.5V to +3.3V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Differential clock inputs (CK0 and CK0#)
• Four internal banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs maximum average periodic refresh interval
MT18VDDT1672G, MT18VDDT3272G
For the latest data sheet, please refer to the Micron
Web site:
www.micron.com/mti/msp/html/
datasheet.html
PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SYMBOL
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DD
Q
DNU
DNU
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
PIN SYMBOL
47
DQS8
48
A0
49
CB2
50
V
SS
51
CB3
52
BA1
53
DQ32
54
V
DD
Q
55
DQ33
56
DQS4
57
DQ34
58
V
SS
59
BA0
60
DQ35
61
DQ40
62
V
DD
Q
63
WE#
64
DQ41
65
CAS#
66
V
SS
67
DQS5
68
DQ42
69
DQ43
70
V
DD
71
DNU
72
DQ48
73
DQ49
74
V
SS
75
DNU
76
DNU
77
V
DD
Q
78
DQS6
79
DQ50
80
DQ51
81
V
SS
82
V
DDID
83
DQ56
84
DQ57
85
V
DD
86
DQS7
87
DQ58
88
DQ59
89
V
SS
90
WP
91
SDA
92
SCL
PIN SYMBOL PIN SYMBOL
93
V
SS
139
V
SS
94
DQ4
140
DQS17
95
DQ5
141
A10
96
V
DD
Q
142
CB6
97
DQS9
143
V
DD
Q
98
DQ6
144
CB7
99
DQ7
145
V
SS
100
V
SS
146
DQ36
101
NC
147
DQ37
102
NC
148
V
DD
103 NC (A13) 149
DQS13
104
V
DD
Q
150
DQ38
105
DQ12
151
DQ39
106
DQ13
152
V
SS
107
DQS10
153
DQ44
108
V
DD
154
RAS#
109
DQ14
155
DQ45
110
DQ15
156
V
DD
Q
111
CKE1
157
S0#
112
V
DD
Q
158 NC (S1#)
113 NC (BA2) 159
DQS14
114
DQ20
160
V
SS
115
NC (A12)
161
DQ46
116
V
SS
162
DQ47
117
DQ21
163
DNU
118
A11
164
V
DD
Q
119
DQS11
165
DQ52
120
V
DD
166
DQ53
121
DQ22
167 NC (FETEN)
122
A8
168
V
DD
123
DQ23
169
DQS15
124
V
SS
170
DQ54
125
A6
171
DQ55
126
DQ28
172
V
DD
Q
127
DQ29
173
NC
128
V
DD
Q
174
DQ60
129
DQS12
175
DQ61
130
A3
176
V
SS
131
DQ30
177
DQS16
132
V
SS
178
DQ62
133
DQ31
179
DQ63
134
CB4
180
V
DD
Q
135
CB5
181
SA0
136
V
DD
Q
182
SA1
137
CK0
183
SA2
138
CK0#
184
V
DDSPD
OPTIONS
• Package
184-pin DIMM (gold)
• Frequency/CAS Latency*
266 MHz/CL = 2
(133 MHz DDR SDRAMs)
266 MHz/CL = 2.5
(133 MHz DDR SDRAMs)
200 MHz/CL = 2
(100 MHz DDR SDRAMs)
MARKING
G
-262
-265
-202
*Device latency only; extra clock cycle required due to input
register.
184-Pin DIMM
NOTE:
Symbols in parentheses are not used on this module
but may be used for other modules in this product
family. They are for reference only.
16, 32 Meg x 72 DDR Registered SDRAM DIMMs
ZM44.p65 – Rev. 4/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
16, 32 MEG x 72
DDR REGISTERED SDRAM DIMMs
KEY DDR SDRAM COMPONENT
TIMING PARAMETERS
MODULE
MARKING
-262
-265
-202
SPEED
GRADE
-7 (7.5ns @ CL = 2)
-7 (7.5ns @ CL = 2.5)
-75 (10ns @ CL = 2)
CLOCK
RATE (1/
t
CK)
133 MHz
143 MHz
100 MHz
*CL = CAS (READ) latency
PART NUMBERS
PART NUMBER
CONFIGURATION SYSTEM BUS SPEED
MT18VDDT1672G-262__
16 Meg x 72
CL = 2, 266 MHz
MT18VDDT1672G-265__
16 Meg x 72
CL = 2.5, 266 MHz
MT18VDDT1672G-202__
16 Meg x 72
CL = 2, 200 MHz
MT18VDDT3272G-262__
32 Meg x 72
CL = 2, 266 MHz
MT18VDDT3272G-265__
32 Meg x 72
CL = 2.5, 266 MHz
MT18VDDT3272G-202__
32 Meg x 72
CL = 2, 200 MHz
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes.
Example: MT18VDDT1672G-262A1
GENERAL DESCRIPTION
The MT18VDDT1672 and MT18VDDT3272 are
high-speed CMOS, dynamic random-access, 128MB
and 256MB memories organized in a x72 configura-
tion. These modules use internally configured quad-
bank DDR SDRAMs.
The DDR SDRAM modules use a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding
n-bit
wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
The DDR SDRAM modules operate from a differen-
tial clock (CK0 and CK0#); the crossing of CK0 going
HIGH and CK0# going LOW will be referred to as the
positive edge of CK0. Commands (address and control
signals) are registered at every positive edge of CK0.
Input data is registered on both edges of DQS, and
16, 32 Meg x 72 DDR Registered SDRAM DIMMs
ZM44.p65 – Rev. 4/00
output data is referenced to both edges of DQS, as well
as to both edges of CK0.
Read and write accesses to the DDR SDRAM mod-
ules are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which
is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM modules provide for program-
mable READ or WRITE burst lengths of 2, 4, or 8
locations. An auto precharge function may be enabled
to provide a self-timed row precharge that is initiated
at the end of the burst access.
As with standard SDR SDRAM modules, the
pipelined, multibank architecture of DDR SDRAM
modules allows for concurrent operation, thereby pro-
viding high effective bandwidth by hiding row precharge
and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more informa-
tion regarding DDR SDRAM operation, refer to the
64Mb and 128Mb x 4 x 4 DDR SDRAM data sheets.
PLL AND REGISTER OPERATION
The DDR SDRAM module is operated in registered
mode where the control/address input signals are latched
in the register on one rising clock edge and sent to the
DDR SDRAM devices on the following rising clock edge
(data access is delayed by one clock). A phase-lock loop
(PLL) on the module is used to redrive the differential
clock signals CK0 and CK0# to the DDR SDRAM devices
to minimize system clock loading.
SERIAL PRESENCE-DETECT OPERATION
The DDR SDRAM module incorporates serial pres-
ence-detect (SPD). The SPD function is implemented
using a 2,048-bit EEPROM. This nonvolatile storage
device contains 256 bytes. The first 128 bytes can be
programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM’s SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
16, 32 MEG x 72
DDR REGISTERED SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT18VDDT1672 (128MB) and MT18VDDT3272 (256MB)
VSS
RS0#
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DM CS# DQS
DQ0
DQ1 U1
DQ2
DQ3
DQS11
DM CS# DQS
DQ0
DQ1 U2
DQ2
DQ3
DQS12
DM CS# DQS
DQ0
DQ1 U3
DQ2
DQ3
DQS13
DM CS# DQS
DQ0
DQ1 U4
DQ2
DQ3
DQS14
DM CS# DQS
DQ0
DQ1 U5
DQ2
DQ3
DQS15
DM CS# DQS
DQ0
DQ1 U6
DQ2
DQ3
DQS16
DM CS# DQS
DQ0
DQ1 U7
DQ2
DQ3
DQS17
DM CS# DQS
DQ0
DQ1 U8
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U17
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U16
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U15
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U14
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U13
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U12
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U11
DQ2
DQ3
DM CS# DQS
DQ0
DQ1 U0
DQ2
DQ3
DQS10
DM CS# DQS
DQ0
DQ1 U10
DQ2
DQ3
DQS9
DQ32
DQ33
DQ34
DQ35
DM CS# DQS
DQ0
DQ1 U9
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS2
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQS3
DQ40
DQ41
DQ41
DQ43
DQ12
DQ13
DQ14
DQ15
DQS4
DQ44
DQ45
DQ46
DQ47
CB0
CB1
CB2
CB3
DQS5
CB4
CB5
CB6
CB7
DQ16
DQ17
DQ18
DQ19
DQS6
DQ48
DQ49
DQ50
DQ51
DQ20
DQ21
DQ22
DQ23
DQS7
DQ52
DQ53
DQ54
DQ55
DQ24
DQ25
DQ26
DQ27
DQS8
DQ56
DQ57
DQ58
DQ59
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
S0#
BA0, BA1
A0-A11
RAS#
CAS#
CKE0
WE#
R
E
G
I
S
T
E
R
S
RS0#
RBA0, RBA1: SDRAMS U0-U17
RA0-RA11: SDRAMS U0-U17
RRAS#: SDRAMS U0-U17
RCAS#: SDRAMS U0-U17
RCKE0: SDRAMS U0-U17
RWE#: SDRAMS U0-U17
SCL
WP
47K
RESET#
V
DDQ
CK0
CK0#
120
PLL
SERIAL PD
SDA
A0
A1
A2
SA0 SA1 SA2
SDRAM X 2
SDRAM X 2
SDRAM X 2
SDRAM X 2
SDRAM X 2
SDRAM X 2
SDRAM X 2
SDRAM X 2
SDRAM X 2
REGISTER X 2
PCK
PCK#
SDRAMS U0-U17
SDRAMS U0-U17
SDRAMS U0-U17
SDRAMS U0-U17
U0-U17 = MT46V16M4A2TG SDRAMs for 128MB
U0-U17 = MT46V32M4A2TG SDRAMS for 256MB
V
DD
V
REF
V
SS
NOTE:
1. All resistor values are 22 ohms unless otherwise specified.
2. Reference designators in this diagram do not necessarily match the actual module.
16, 32 Meg x 72 DDR Registered SDRAM DIMMs
ZM44.p65 – Rev. 4/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
16, 32 MEG x 72
DDR REGISTERED SDRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
63, 65, 154
137, 138
SYMBOL
WE#, CAS#,
RAS#
CK0, CK0#
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS# and WE# (along with
S0#, S1#) define the command being entered.
Clock: CK0 and CK0# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK0 and negative
edge of CK0#. Output data (DQs and DQS) is
referenced to the crossings of CK0 and CK0#.
Clock Enable: CKE0 and CKE1 activate (HIGH) and
deactivate (LOW) internal clock signals, and device
input buffers and output drivers. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any bank). CKE0 and CKE1 are
synchronous for all functions except for disabling
outputs, which is achieved asynchronously. CKE0 and
CKE1 must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK0, CK0# and
CKE) are disabled during POWER-DOWN. Input buffers
(excluding CKE0 and CKE1) are disabled during SELF
REFRESH. CKE0 and CKE1 are SSTL_2 inputs but will
detect an LVCMOS LOW level after V
DD
is applied.
No Connect: These pins should be left unconnected.
Chip Select: S0# enables (registered LOW) and disables
(registered HIGH) the command decoder. All com-
mands are masked when S0# is registered HIGH. S0#
provides for external bank selection on systems with
multiple banks. S0# is considered part of the command
code.
Bank Address: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE or PRECHARGE command is
being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE
command (column-address A0-A8, with A10 defining
auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled
during a PRECHARGE command to determine whether
the PRECHARGE applies to one bank (A10 LOW) or all
banks (A10 HIGH). The address inputs also provide the
op-code during a MODE REGISTER SET command.
SSTL_2 reference voltage.
V
DD
identification flag.
Write Protect: Serial presence-detect hardware write
protect.
21, 111
CKE0, CKE1
Input
9, 101, 102, 103, 113,
115, 158, 167, 173
157
NC
S0#
—
Input
59, 52
BA0, BA1
Input
48, 43, 41, 130, 37, 32,
125, 29, 122, 27, 141,
118
A0-A11
Input
1
82
90
V
REF
V
DDID
WP
Input
Input
Input
16, 32 Meg x 72 DDR Registered SDRAM DIMMs
ZM44.p65 – Rev. 4/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
16, 32 MEG x 72
DDR REGISTERED SDRAM DIMMs
PIN DESCRIPTIONS (continued)
PIN NUMBERS
92
SYMBOL
SCL
TYPE
Input
DESCRIPTION
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs: These pins are used
to configure the presence-detect device.
Asynchronously forces all register outputs LOW when
RESET# is LOW. This signal can be used during power-
up to ensure CKE0/1 are LOW and SDRAM DQs are
High-Z.
Data I/Os: Check bits.
Data Strobes: Output with READ data, input with
WRITE data Edge-aligned with READ data, centered
in WRITE data. Used to capture WRITE data.
Data I/Os: Data bus.
181, 182, 183
10
SA0-SA2
RESET#
Input
Input
44, 45, 49, 51, 134, 135,
142, 144
5, 14, 25, 36, 47, 56, 67,
78, 86, 97, 107, 119, 129,
140, 149, 159, 169, 177
2, 4, 6, 8, 12, 13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
91
CB0-CB7
DQS0-DQS17
Input/
Output
Input/
Output
Input/
Output
DQ0-DQ63
SDA
Input/
Output
Supply
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and out of
the presence-detect portion of the module.
DQ Power Supply: +2.5V +0.2V.
15, 22, 30, 54, 62, 77, 96,
104, 112, 128, 136, 143,
156, 164, 172, 180
7, 38, 46, 70, 85, 108,
120, 148, 168
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93,
100, 116, 124, 132, 139,
145, 152, 160, 176
184
16, 17, 71, 75, 76, 163
V
DD
Q
V
DD
V
SS
Supply
Supply
Power Supply: +2.5V +0.2V.
Ground.
V
DDSPD
DNU
Supply
–
Serial EEPROM positive power supply.
Do Not Use: These pins are not connected on this
module but are assigned pins on other modules in
this product family.
16, 32 Meg x 72 DDR Registered SDRAM DIMMs
ZM44.p65 – Rev. 4/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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