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ZPSD401A2V-25JI

Description
Parallel I/O Port, 40 I/O, CMOS, PQCC68,
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size5MB,108 Pages
ManufacturerWaferscale Integration Inc.
Download Datasheet Parametric View All

ZPSD401A2V-25JI Overview

Parallel I/O Port, 40 I/O, CMOS, PQCC68,

ZPSD401A2V-25JI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerWaferscale Integration Inc.
Reach Compliance Codeunknown
Maximum access time2.5e-7 ns
Other featuresGENERAL PURPOSE ZPLD
maximum clock frequency33.33 MHz
External data bus width16
JESD-30 codeS-PQCC-J68
JESD-609 codee0
Number of I/O lines40
Number of ports5
Number of terminals68
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3 V
Certification statusNot Qualified
ROM size (bits)256 Bits
Maximum standby current0.000005 A
Maximum supply voltage5.5 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
UV erasableN
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
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