White Electronic
512Kx32 SRAM Module.3.3V
FEATURES
DSP Memory Solution
ADSP-21060L (SHARC)
ADSP-21062L (SHARC)
Texas Instruments TMS320LC31
RISC Memory Solution
MPC860 (Power Quic)
Random Access Memory Array
Fast Access Times: 12, 15, 17, and 20ns
Individual Byte Enables
User configuration organization with Minimal
Additional Logic
Master Output Enable and Write Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Surface Mount Package
68 Lead PLCC, No. 99 JEDEC MO-47AE
Small Footprint, 0.990 Sq. In.
Multiple Ground Pins for Maximum Noise
Immunity
Single +3.3V (±5%) Supply Operation
EDI8F32512V
DESCRIPTION
The EDI8F32512V is a high speed, 3.3V, 16 megabit SRAM.
The device is available with access times of 12, 15, 17 and
20ns allowing the creation of a no wait state DSP and RISC
microprocessor memory solutions.
The device can be configured as a 512K x 32 and used to
create a single chip external data memory solution for TI's
TMS320LC31 (figure 5), or Analog's SHARC
TM
DSP (figure
6).
The device provides a 56% space savings when compared
to four 512Kx8, 36 pin SOJs. In addition the EDI8K32512V
has only a 10pF load on the data lines vs. 32 pF for four
plastic SOJs.
The device provides a memory upgrade of the EDI8F32256V
(256K x 32) or the EDI8L32128V (128K x 32) (figure 8).
Alternatively, the device's chip enables can configure it as
a 1M x 16. A 1M x 48 program memory array for Analog's
CHARC DSP is created using three devices (figure 7).
If
this memory is too deep, two 512K x 24s (EDI8L24512V)
can be used to create a 512K x 48 array or two 128K x
24s (EDI8L24128V) can be used to create a 128K x 48
array.
Note: Soldier Reflow Temperature should not exceed 260°C for 10 seconds.
FIG. 1
PIN CONFIGURATIONS
DQ16
A18
A17
E3#
E2#
E1#
E0#
NC
V
CC
NC
NC
G#
W#
A16
A15
A14
DQ15
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
PIN DESCRIPTION
A0-A18
E0#-E3#
W#
G#
DQ0-DQ31
V
CC
V
SS
NC
Address Inputs
Chip Enables
(One per Byte)
Master Write Enable
Master Output Enable
Common Data
Input/Output
Power (+3.3V±5%)
Ground
No Connectiona
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
CC
DQ24
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
V
CC
DQ7
DQ6
DQ5
DQ4
V
SS
DQ3
DQ2
DQ1
BLOCK DIAGRAM
A0-18
G#
W#
E0#
E1#
E2#
E3#
1
19
512K x 32
Memory
Array
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October. 2000
Rev. 3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
DQ31
A6
A5
A4
A3
A2
A1
A0
V
CC
A13
A12
A11
A10
A9
A8
A7
DQ0
White Electronic
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to V
SS
Operating Temperature t
A
(Ambient)
Commercial
Industrial
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, t
J
-0.5V to 7.0V
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
2.5 Watts
20 mA
-175°C
EDI8F32512V
RECOMMENDED DC OPERATING
CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Sym
V
CC
V
SS
V
IH
V
IL
Min
3.135
0
2.2
-0.3
Typ
3.3
0
--
--
Max
3.465
0
V
CC
+ 0.3
+0.8
Units
V
V
V
V
CAPACITANCE
(f=1.0MHz, V
IN
=V
CC
or V
SS
)
Parameter
Address Lines
Data Lines
Chip Enable Line
Write & Output Enable Line
Sym
CI
CD/Q
E0-3
W#, G#
Max
30
10
8
30
Unit
pF
pF
pF
pF
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this speci
fi
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
TRUTH TABLE
E#
H
L
L
L
W#
X
H
H
L
G#
X
H
L
X
Mode
Standby
Output
Deselect
Read
Write
Output
HIGH Z
HIGH Z
D
OUT
D
IN
Power
I
CC
2, I
CC
3
I
CC
1
I
CC
1
I
CC
1
(V
CC
= 3.3V, t
A
= 25°C)
Parameter
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power CMOS Supply
Current
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Sym
I
CC
1
I
CC
2
I
CC
3
I
LI
I
LO
V
OH
V
OL
Conditions
W# = V
IL
, II/O = 0mA, Min Cycle
E# > V
IH
, V
IN
< V
IL
or V
IN
> V
IH
E# > V
CC
-0.2V
V
IN
> V
CC
=0.2V or V
IN
< 0.2V
V
IN
= 0V to V
CC
V I/O = 0V TO V
CC
I
OH
= -4.0mA
I
OL
= 4.0mA
DC ELECTRICAL CHARACTERISTICS
12 & 15
Min
--
--
--
--
--
2.4
--
Typ
440
100
60
--
--
--
--
Max
800
300
80
±20
±20
--
0.4
Min
--
--
--
--
--
2.4
--
17 & 20
Typ
440
100
60
--
--
--
--
Max
640
200
100
±10
±10
--
0.4
Units
mA
mA
mA
μA
μA
V
V
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
V
SS
to 3.0V
5ns
1.5V
Figure 1
(Note: For t
EHQZ
,t
GHQZ
and t
WLQZ
, CL = 5pF, Figure 2)
Q
255Ω
30pF
Q
255Ω
5pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October. 2000
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
AC CHARACTERISTICS READ CYCLE
(V
CC
= 3.3V, V
SS
= 0V, t
A
= 0°C to -70°C)
Symbol
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High (1)
JEDEC
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
Alt.
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
Min
12
12ns
Max
12
10
3
6
3
6
3
6
3
7
3
7
3
8
3
7
3
8
Min
15
15ns
Max
15
12
3
8
Min
17
17ns
Max
17
15
EDI8F32512V
20ns
Min
20
Max
20
20
3
9
3
9
3
9
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 1. Parameter is guaranteed by design but not tested.
AC CHARACTERISTICS WRITE CYCLE
(V
CC
= 3.3V, V
SS
= 0V, t
A
= 0°C to -70°C)
Symbol
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
JEDEC
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AHEH
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
Alt.
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
Min
12
8
8
0
0
8
8
8
8
0
0
0
0
0
6
6
3
12ns
Max
Min
15
10
10
0
0
10
10
10
10
0
0
0
0
0
7
7
3
15ns
Max
Min
17
11
11
0
0
11
11
11
11
0
0
0
0
0
8
8
3
17ns
Max
Min
20
12
12
0
0
12
12
12
12
0
0
0
0
0
9
9
3
20ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
7
8
9
Notes: 1. Parameter guaranteed, but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October. 2000
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
FIG. 2
TIMING WAVEFRONT - READ CYCLE
EDI8F32512V
t
AVAV
A
ADDRESS 1
ADDRESS 2
t
AVQV
Q
t
AVQX
DATA
1
DATA 2
READ CYCLE 1 (W# HIGH; G#, E# LOW)
FIG. 2
TIMING WAVEFRONT - READ CYCLE
t
AVAV
A
t
AVQV
E#
t
ELQV
t
ELQX
G#
t
EHQZ
t
GLQV
t
GLQX
Q
t
GHQZ
READ CYCLE 2 (W# HIGH)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October. 2000
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic
FIG. 3
WRITE CYCLE - W# CONTROLLED
t
AVAV
A
EDI8F32512V
t
AVWH
t
ELWH
E#
t
WHAX
t
AVWL
W#
t
WLWH
t
DVWH
t
WHDX
D
DATA VALID
t
WLQZ
Q
HIGH Z
t
WHQX
WRITE CYCLE 1, W# CONTROLLED
FIG. 4
WRITE CYCLE - E# CONTROLLED
t
AVAV
A
t
AVEH
t
ELEH
E#
t
EHAX
t
AVEL
W#
t
WLEH
t
DVEH
t
EHDX
D
Q
HIGH Z
DATA VALID
WRITE CYCLE 2, E# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October. 2000
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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