DATA SHEET
BIPOLAR DIGITAL INTEGRATED CIRCUITS
P
PB1506GV,
P
PB1507GV
3GHz INPUT DIVIDE BY 256, 128, 64 PRESCALER IC
FOR ANALOG DBS TUNERS
The
P
PB1506GV and
P
PB1507GV are 3.0 GHz input, high division silicon prescaler ICs for analog DBS tuner
applications. These ICs divide-by-256, 128 and 64 contribute to produce analog DBS tuners with kit-use of 17 K
series DTS controller or standard CMOS PLL synthesizer IC. The
P
PB1506GV/
P
PB1507GV are shrink package
versions of the
P
PB586G/588G or
P
PB1505GR so that these smaller packages contribute to reduce the mounting
space replacing from conventional ICs.
The
P
PB1506GV and
P
PB1507GV are manufactured using NEC’s high f
T
NESAT™IV silicon bipolar process.
This process uses silicon nitride passivation film and gold electrodes. These materials can protect chip surface from
external pollution and prevent corrosion/migration. Thus, these ICs have excellent performance, uniformity and
reliability.
FEATURES
x
x
x
x
x
High toggle frequency
Low current consumption
Selectable high division
Pin connection variation
: f
in
= 0.5 GHz to 3.0 GHz
: 5 V, 19 mA
:
y256, y128, y64
:
P
PB1506GV and
P
PB1507GV
High-density surface mounting : 8-pin plastic SSOP (175 mil)
APPLICATION
These ICs can use as a prescaler between local oscillator and PLL frequency synthesizer included modulus
prescaler. For example, following application can be chosen;
x
x
Analog DBS tuner’s synthesizer
Analog CATV converter synthesizer
ORDERING INFORMATION
PART NUMBER
PACKAGE
8-pin plastic
SSOP (175 mil)
MARKING
1506
1507
SUPPLYING FORM
Embossed tape 8 mm wide. Pin 1 is in tape pull-out
direction. 1 000 p/reel.
P
PB1506GV-E1
P
PB1507GV-E1
Remarks
To order evaluation samples, please contact your local NEC sales office.
(Part number for sample order:
P
PB1506GV,
P
PB1507GV)
Caution: Electro-static sensitive devices
Document No. P10767EJ3V0DS00 (3rd edition)
Date Published January 1998 N CP(K)
Printed in Japan
©
1996
P
PB1506GV,
P
PB1507GV
PIN CONNECTION (Top View)
Pin
NO.
1
2
7
1
8
P
PB1506GV
SW1
IN
IN
GND
NC
SW2
OUT
V
CC
P
PB1507GV
IN
V
CC
SW1
OUT
GND
SW2
NC
IN
2
3
3
6
4
5
4
5
6
7
8
PRODUCT LINE-UP
Features
(division, Freq.)
y512, y256,
2.5 GHz
y128, y64,
2.5 GHz
y256, y128, y64
3.0 GHz
Part No.
I
CC
(mA)
28
26
14
19
19
f
in
(GHz)
0.5 to 2.5
0.5 to 2.5
0.5 to 3.0
0.5 to 3.0
0.5 to 3.0
V
CC
(V)
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
4.5 to 5.5
8 pin SSOP 175 mil
Standard
NEC original
Standard
Package
Pin connection
P
PB586G
P
PB588G
P
PB1505GR
P
PB1506GV
P
PB1507GV
8 pin SOP 225 mil
NEC original
Remarks
x
This table shows the TYP values of main parameters.
CHARACTERISTICS.
Please refer to ELECTRICAL
x
P
PB586G and
P
PB588G are discontinued.
INTERNAL BLOCK DIAGRAM
D
IN
IN
CLK
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
CLK Q
Q
Q
Q
Q
D
CLK
Q
D
CLK
Q
D
CLK
Q
OUT
Q
AMP
Q
Q
SW1
SW2
2
P
PB1506GV,
P
PB1507GV
SYSTEM APPLICATION EXAMPLE
RF unit block of Analog DBS tuners
1stIF input
from DBS converter
BPF
To 2150 MHz
MIX
SAW
AGC amp.
FM demo.
Baseband output
OSC
To 2650 MHz
High division prescaler
µ
PB1506GV or
µ
PB1507GV
CMOS
PLL
synthesizer
LPF
loop filter
RF unit block of Analog CATV converter
To 800 MHz
BPF
upconverter
downconverter
BPF
To 1300 MHz
OSC
To 2000 MHz
High division prescaler
µ
PB1506GV or
µ
PB1507GV
CMOS
PLL
synthesizer
LPF
loop filter
3
P
PB1506GV,
P
PB1507GV
PIN EXPLANATION
Applied
voltage
V
•
•
Pin
voltage
V
2.9
Pin no.
Pin name
IN
Functions and explanation
Signal input pin. This pin should be coupled to signal
source with capacitor (e.g. 1 000 pF) for DC cut.
Signal input bypass pin. This pin must be equipped
with bypass capacitor (e.g. 1 000 pF) to minimize
ground impedance.
Ground pin. Ground pattern on the board should be
formed as wide as possible to minimize ground
impedance.
Divide ratio input pin. The ratio can be determined by
following applied level to these pins.
SW2
H
L
y128
y256
P
PB1506GV
2
P
PB1507GV
1
IN
2.9
3
8
GND
0
•
4
5
SW1
H/L
•
1
3
SW2
SW1
H
L
y64
y128
6
6
These pins should be equipped with bypass capacitor
(e.g. 1 000 pF) to minimize ground impedance.
V
CC
4.5 to 5.5
•
Power supply pin. This pin must be equipped with
bypass capacitor (e.g. 10 000 pF) to minimize ground
impedance.
Divided frequency output pin. This pin is designed as
emitter follower output. This pin can be connected to
CMOS input due to 1.2 V
P-P
MIN output.
Non connection pin. This pin must be openned.
8
2
OUT
•
2.6 to 4.7
7
4
NC
•
•
5
7
4
P
PB1506GV,
P
PB1507GV
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage
Input voltage
Total power dissipation
SYMBOL
V
CC
V
in
P
D
T
A
= +25
qC
T
A
= +25
qC
Mounted on double sided copper clad
50
u
50
u
1.6 mm epoxy glass PWB (T
A
=
+85
qC)
CONDITION
RATINGS
ð0.5
to +6.0
ð0.5
to V
CC
+ 0.5
250
UNIT
V
V
mW
Operating ambient temperature
Storage temperature
T
A
T
stg
ð40
to +85
ð55
to +150
qC
qC
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage
Operating ambient temperature
SYMBOL
V
CC
T
A
MIN.
4.5
ð40
TYP.
5.0
+25
MAX.
5.5
+85
UNIT
V
qC
NOTICE
ELECTRICAL CHARACTERISTICS (T
A
=
ð
40 to +85
q
C, V
CC
= 4.5 to 5.5 V, Z
S
= 50
:
)
PARAMETER
Circuit current
Upper limit operating frequency
Lower limit operating frequency 1
Lower limit operating frequency 2
Input power 1
Input power 2
Output Voltage
Divide ratio control input high
SYMBOL
I
CC
f
in(u)
f
in(L)1
f
in(L)2
P
in1
P
in2
V
out
V
IH1
TEST CONDITION
No signals
P
in
=
ð15
to +6 dBm
P
in
=
ð10
to +6 dBm
P
in
=
ð15
to +6 dBm
f
in
= 1.0 to 3.0 GHz
f
in
= 0.5 to 1.0 GHz
C
L
= 8 pF
Connection in the test
circuit
Connection in the test
circuit
Connection in the test
circuit
Connection in the test
circuit
MIN.
12.5
3.0
•
•
ð15
ð10
1.2
V
CC
TYP.
19
•
•
•
•
•
1.6
V
CC
MAX.
26.5
•
0.5
1.0
+6
+6
•
V
CC
UNIT
mA
GHz
GHz
GHz
dBm
dBm
V
P-P
Divide ratio control input low
V
IL1
OPEN or
GND
V
CC
OPEN or
GND
V
CC
OPEN or
GND
V
CC
Divide ratio control input high
V
IH2
Divide ratio control input low
V
IL2
OPEN or
GND
OPEN or
GND
OPEN or
GND
5
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