NEC’s LOW POWER
GPS RF RECEIVER
BIPOLAR ANALOG + INTEGRATED CIRCUIT
UPB1009K
DESCRIPTION
The
µ
PB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF
filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption
is low.
Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable
with an on-chip divider is possible.
NEC’s stringent quality assurance and test procedures ensure the highest reliability and performance.
FEATURES
• Double conversion
• Multiple system clocks
• A/D converter
• High-density RF block
• Supply voltage
• Low current consumption
• High-density surface mountable
: f
REFin
= 16.368 MHz, f
1stIFin
= 61.380 MHz, f
2ndIFin
= 4.092 MHz
: f
REFin
= 14.4, 16.384, 19.2, 26 MHz, f
1stIFin
= 62.980 MHz, f
2ndIFin
= 2.556 MHz
: On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096)
: On-chip 4-bit A/D converter
: On-chip VCO tank circuit and 2ndIF filter
: V
CC
= 2.7 to 3.3 V
: I
CC
= 26.0 mA TYP. @ V
CC
= 3.0 V, N = 100
: 44-pin plastic QFN
APPLICATIONS
• Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz
• Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
UPB1009K
ORDERING INFORMATION
Part Number
Package
44-pin plastic QFN
Supplying Form
•
12 mm wide embossed taping
•
Pin 1 indicates pull-out direction of tape
•
Qty 1.5 kpcs/reel, Dry pack specification
µ
PB1009K-E1
Remark
To order evaluation samples, contact your nearby sales office.
Part number for sample order:
µ
PB1009K
2
UPB1009K
PRODUCT LINE-UP (T
A
= +25°C, V
CC
= 3.0 V)
Type
Part Number
Functions
(Frequency unit: MHz)
Pre-amplifier + RF/IF down-
converter + PLL synthesizer
REF = 16.368
1stIF = 61.380/2ndIF = 4.092
REF = 14.4, 16.384, 19.2, 26
1stIF = 62.980/2ndIF = 2.556
On-chip 4-bit ADC
V
CC
(V)
2.7 to 3.3
I
CC
(mA)
26.0
CG
(dB)
Package
Status
Clock
µ
PB1009K
Frequency
Specific
1 chip IC
44-pin plastic QFN
New Device
µ
PB1008K
2.7 to 3.3
LNA + Pre-amplifier + RF/IF
down-converter + PLL
synthesizer
REF = 27.456
1stIF = 175.164/2ndIF = 0.132
On-chip 2-bit ADC
Pre-amplifier + RF/IF down-
converter + PLL synthesizer
REF = 16.368
1stIF = 61.380/2ndIF = 4.092
REF = 16.368
1stIF = 61.380/2ndIF = 4.092
2.7 to 3.3
18.0
100 to
120
36-pin plastic QFN
µ
PB1007K
25.0
100 to
120
36-pin plastic QFN
Available
µ
PB1005K
36-pin plastic QFN
Remark
Typical performance. Please refer to
ELECTRICAL CHARACTERISTICS
in detail.
SYSTEM APPLICATION EXAMPLE
GPS receiver RF block diagram
PD1 and PD2 in the figure are Power Save Mode control pins.
MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins.
1stIF =
61.38 MHz
62.98 MHz
IF SAW
RF =
1575.42 MHz
1stLo =
1636.8 MHz
1638.4 MHz
Pre- 1st.
amp mix
2ndIF =
4.092 MHz
2.556 MHz
IF
Amp
–
+
+
–
DC trim
RF
LNA SAW
2nd
MIX
RF
AGC
LPF
IF
÷25
4bit
ADC
Para Data
Regulator
PD1
÷N
Tank
Cont.
PLL
–
+
Samp Clk
AGC cont
PD2
MS1 MS2
TCXO
Caution This diagram schematically shows only the
µ
PB1009K’s internal functions on the system.
This diagram does not present the actual application circuits.
GPS baseband
3
UPB1009K
PIN CONNECTION AND INTERNAL BLOCK DIAGRAM
GNDsub
AGCout
V
DD
buf
AGCin
SCKin
GNDbuf
23
22 GNDana
–
–
D3
D2
D1
33
V
DD
logi 34
GNDlogi 35
PD1 36
PD2 37
1stIFin 38
IFV
CC
39
32
31
30
29
28
27
D0
26
25
24
V
DD
ana
+
+
4bit ADC
+
–
21 DCOFFin
20 DCOFFout
19 2ndIFin
Pwdctrl
Logic
V
GC
LPF
IFamp
1/4
18 2ndIFout
17 IFGND
1st IFout 41
LNAV
CC
42
LNAGND 43
PreAmp
LNAin 44
1
2
3
4
1stMIX
65/1024
9/256
1stMIXV
CC
40
16 CLKout
15 PLLGND
PLL
PD
Fref
14 PLLV
CC
1/25
3/64
OSC
CP
5
6
7
8
9
10
11
13 Refin
12 MS2
1stMIXin
LOV
CC
V
CO1
LNAout
RegGND
GND
(1st-MIX)
MS1
Rext
V
CO2
LOGND
4
CPout
UPB1009K
PIN EXPLANATION
Pin
No.
1
2
Pin Name
Function and Application
Internal Equivalent Circuit
PreAMPout
Rext
Output pin of preamplifier.
Connect a resistor for the reference
constant-current power supply to this pin.
Ground this pin at 22 kΩ.
Ground pin for regulator.
Power supply voltage pin for preamplifier.
Connect a bypass capacitor to this pin to
reduce the high-frequency impedance.
Ground pin of preamplifier.
Input pin of preamplifier.
1
42
3
42
RegGND
PreAmpV
CC
Regulator
44
2
43
44
PreAmpGND
PreAmpin
43
3
4
5
40
1stMIXin
1stMIXGND
1stMIXV
CC
1stMIX input pin.
Ground pin for first MIX.
Power supply voltage pin for RF mixer.
Connect a bypass capacitor to this pin to
reduce the high-frequency impedance.
Output pin of RF mixer. Insert an IFSAW
filter between this pin and pin 37. The
VCO oscillation signal can be monitored on
this pin.
40
Gibert
Cell
4
41
41
1stIFout
Bias
5
5
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